last updated: 26/03/19
Song of this chapter: Supertramp > Breakfast in America > The logical song
In sequential logic the output depends on the present input but also on the history of the input. Sequential logic has memory!.
Modern computing would not be possible without sequential logic (memory). Most circuits are a mixture of combinational and sequential logic.
We distinguish synchronous and asynchronous circuits in digital sequential logic. Synchronous circuits have a clock signal and the state of the device changes only if the clock signal changes. Asynchronous circuits respond to changing inputs.
Let's begin with the basic circuit named
flip-flop. Flip-flops can be asynchronous (transparent, level triggered) or synchronous (clocked). Commonly the more simple asynchronous flip-flops are named
latches. The synchronous flip-flops using a clock signal are named
In asynchronous sequential logic we don't find a clock signal. A changing level at an input triggers with a very short delay a reaction of an output level. The very short delay depends of the manufacturing process, the temperature, the complexity of the circuit etc. and is never equal for two circuits. If we combine two incoming signals and one signal comes slightly later than the other, the state the receiving circuit goes into will depend on which signal gets to the gate first. Depending on very small differences in the delays the circuit can go into the wrong state. This is called a race condition.
Asynchronous sequential logic can be faster than synchronous logic because it must not wait for the clock signal, but is used only in a few critical circuits relying on speed as small parts of microprocessors and digital signal processing circuits.
Asynchronous logic is difficult to design and problematic to use, so normally only synchronous circuits with clock signal are used in devices and computers. So why a chapter on latches? They provide the possibility to fill the gap between combinational logic and synchronous sequential logic. Latches are building blocks of sequential circuits. They are build from logic gates and they help to understand how synchronous circuits work.
The latch is a memory element. Memory can only be created with a feedback from the output to the input.
The two inputs of the latch are named
Reset, thus SR-latch. Let's look at a very simple circuit to understand how it works, the SR AND-OR latch:
First we omit the feedback line and will successively change the states, keeping in mind, that the F input takes the state of the Q output.
|0||0|||||0||0||system idle (at rest)|
||output Q stays HIGH|
||system idle: Q stays HIGH even when S goes back to LOW (memory!)|
||output Q stays LOW|
||system idle: Q stays LOW even when R goes back to LOW (memory!)|
F = Q let's draw the feedback line:
If we look as our table we see that Q is HIGH if S OR (NOT R AND F) The Boolean formula for this circuit will be:
This circuit is for learning purpose, because real latches are not build from 3 different gates. Let's change the circuit to
NOR only or
NAND only gates:
Let's first replace the
AND using the De Morgan law: