L152RE_blink_no_board.elf: file format elf32-littlearm Sections: Idx Name Size VMA LMA File off Algn 0 .isr_vector 0000013c 08000000 08000000 00010000 2**0 CONTENTS, ALLOC, LOAD, READONLY, DATA 1 .text 00001714 0800013c 0800013c 0001013c 2**2 CONTENTS, ALLOC, LOAD, READONLY, CODE 2 .rodata 0000001c 08001850 08001850 00011850 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 3 .ARM.extab 00000000 0800186c 0800186c 0002000c 2**0 CONTENTS 4 .ARM 00000008 0800186c 0800186c 0001186c 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 5 .preinit_array 00000000 08001874 08001874 0002000c 2**0 CONTENTS, ALLOC, LOAD, DATA 6 .init_array 00000004 08001874 08001874 00011874 2**2 CONTENTS, ALLOC, LOAD, DATA 7 .fini_array 00000004 08001878 08001878 00011878 2**2 CONTENTS, ALLOC, LOAD, DATA 8 .data 0000000c 20000000 0800187c 00020000 2**2 CONTENTS, ALLOC, LOAD, DATA 9 .bss 00000020 2000000c 08001888 0002000c 2**2 ALLOC 10 ._user_heap_stack 00000604 2000002c 08001888 0002002c 2**0 ALLOC 11 .ARM.attributes 00000029 00000000 00000000 0002000c 2**0 CONTENTS, READONLY 12 .debug_info 0000335d 00000000 00000000 00020035 2**0 CONTENTS, READONLY, DEBUGGING 13 .debug_abbrev 00000d69 00000000 00000000 00023392 2**0 CONTENTS, READONLY, DEBUGGING 14 .debug_aranges 000003e8 00000000 00000000 00024100 2**3 CONTENTS, READONLY, DEBUGGING 15 .debug_ranges 00000360 00000000 00000000 000244e8 2**3 CONTENTS, READONLY, DEBUGGING 16 .debug_macro 00013fc2 00000000 00000000 00024848 2**0 CONTENTS, READONLY, DEBUGGING 17 .debug_line 00003d3d 00000000 00000000 0003880a 2**0 CONTENTS, READONLY, DEBUGGING 18 .debug_str 0007d553 00000000 00000000 0003c547 2**0 CONTENTS, READONLY, DEBUGGING 19 .comment 0000007b 00000000 00000000 000b9a9a 2**0 CONTENTS, READONLY 20 .debug_frame 00000e0c 00000000 00000000 000b9b18 2**2 CONTENTS, READONLY, DEBUGGING Disassembly of section .text: 0800013c <__do_global_dtors_aux>: 800013c: b510 push {r4, lr} 800013e: 4c05 ldr r4, [pc, #20] ; (8000154 <__do_global_dtors_aux+0x18>) 8000140: 7823 ldrb r3, [r4, #0] 8000142: b933 cbnz r3, 8000152 <__do_global_dtors_aux+0x16> 8000144: 4b04 ldr r3, [pc, #16] ; (8000158 <__do_global_dtors_aux+0x1c>) 8000146: b113 cbz r3, 800014e <__do_global_dtors_aux+0x12> 8000148: 4804 ldr r0, [pc, #16] ; (800015c <__do_global_dtors_aux+0x20>) 800014a: f3af 8000 nop.w 800014e: 2301 movs r3, #1 8000150: 7023 strb r3, [r4, #0] 8000152: bd10 pop {r4, pc} 8000154: 2000000c .word 0x2000000c 8000158: 00000000 .word 0x00000000 800015c: 08001838 .word 0x08001838 08000160 : 8000160: b508 push {r3, lr} 8000162: 4b03 ldr r3, [pc, #12] ; (8000170 ) 8000164: b11b cbz r3, 800016e 8000166: 4903 ldr r1, [pc, #12] ; (8000174 ) 8000168: 4803 ldr r0, [pc, #12] ; (8000178 ) 800016a: f3af 8000 nop.w 800016e: bd08 pop {r3, pc} 8000170: 00000000 .word 0x00000000 8000174: 20000010 .word 0x20000010 8000178: 08001838 .word 0x08001838 0800017c <__aeabi_uldivmod>: 800017c: b953 cbnz r3, 8000194 <__aeabi_uldivmod+0x18> 800017e: b94a cbnz r2, 8000194 <__aeabi_uldivmod+0x18> 8000180: 2900 cmp r1, #0 8000182: bf08 it eq 8000184: 2800 cmpeq r0, #0 8000186: bf1c itt ne 8000188: f04f 31ff movne.w r1, #4294967295 ; 0xffffffff 800018c: f04f 30ff movne.w r0, #4294967295 ; 0xffffffff 8000190: f000 b974 b.w 800047c <__aeabi_idiv0> 8000194: f1ad 0c08 sub.w ip, sp, #8 8000198: e96d ce04 strd ip, lr, [sp, #-16]! 800019c: f000 f806 bl 80001ac <__udivmoddi4> 80001a0: f8dd e004 ldr.w lr, [sp, #4] 80001a4: e9dd 2302 ldrd r2, r3, [sp, #8] 80001a8: b004 add sp, #16 80001aa: 4770 bx lr 080001ac <__udivmoddi4>: 80001ac: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 80001b0: 468c mov ip, r1 80001b2: 4604 mov r4, r0 80001b4: 9e08 ldr r6, [sp, #32] 80001b6: 2b00 cmp r3, #0 80001b8: d14b bne.n 8000252 <__udivmoddi4+0xa6> 80001ba: 428a cmp r2, r1 80001bc: 4615 mov r5, r2 80001be: d967 bls.n 8000290 <__udivmoddi4+0xe4> 80001c0: fab2 f282 clz r2, r2 80001c4: b14a cbz r2, 80001da <__udivmoddi4+0x2e> 80001c6: f1c2 0720 rsb r7, r2, #32 80001ca: fa01 f302 lsl.w r3, r1, r2 80001ce: fa20 f707 lsr.w r7, r0, r7 80001d2: 4095 lsls r5, r2 80001d4: ea47 0c03 orr.w ip, r7, r3 80001d8: 4094 lsls r4, r2 80001da: ea4f 4e15 mov.w lr, r5, lsr #16 80001de: fbbc f7fe udiv r7, ip, lr 80001e2: fa1f f885 uxth.w r8, r5 80001e6: fb0e c317 mls r3, lr, r7, ip 80001ea: fb07 f908 mul.w r9, r7, r8 80001ee: 0c21 lsrs r1, r4, #16 80001f0: ea41 4303 orr.w r3, r1, r3, lsl #16 80001f4: 4599 cmp r9, r3 80001f6: d909 bls.n 800020c <__udivmoddi4+0x60> 80001f8: 18eb adds r3, r5, r3 80001fa: f107 31ff add.w r1, r7, #4294967295 ; 0xffffffff 80001fe: f080 811c bcs.w 800043a <__udivmoddi4+0x28e> 8000202: 4599 cmp r9, r3 8000204: f240 8119 bls.w 800043a <__udivmoddi4+0x28e> 8000208: 3f02 subs r7, #2 800020a: 442b add r3, r5 800020c: eba3 0309 sub.w r3, r3, r9 8000210: fbb3 f0fe udiv r0, r3, lr 8000214: fb0e 3310 mls r3, lr, r0, r3 8000218: fb00 f108 mul.w r1, r0, r8 800021c: b2a4 uxth r4, r4 800021e: ea44 4403 orr.w r4, r4, r3, lsl #16 8000222: 42a1 cmp r1, r4 8000224: d909 bls.n 800023a <__udivmoddi4+0x8e> 8000226: 192c adds r4, r5, r4 8000228: f100 33ff add.w r3, r0, #4294967295 ; 0xffffffff 800022c: f080 8107 bcs.w 800043e <__udivmoddi4+0x292> 8000230: 42a1 cmp r1, r4 8000232: f240 8104 bls.w 800043e <__udivmoddi4+0x292> 8000236: 3802 subs r0, #2 8000238: 442c add r4, r5 800023a: ea40 4007 orr.w r0, r0, r7, lsl #16 800023e: 2700 movs r7, #0 8000240: 1a64 subs r4, r4, r1 8000242: b11e cbz r6, 800024c <__udivmoddi4+0xa0> 8000244: 2300 movs r3, #0 8000246: 40d4 lsrs r4, r2 8000248: e9c6 4300 strd r4, r3, [r6] 800024c: 4639 mov r1, r7 800024e: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 8000252: 428b cmp r3, r1 8000254: d909 bls.n 800026a <__udivmoddi4+0xbe> 8000256: 2e00 cmp r6, #0 8000258: f000 80ec beq.w 8000434 <__udivmoddi4+0x288> 800025c: 2700 movs r7, #0 800025e: e9c6 0100 strd r0, r1, [r6] 8000262: 4638 mov r0, r7 8000264: 4639 mov r1, r7 8000266: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 800026a: fab3 f783 clz r7, r3 800026e: 2f00 cmp r7, #0 8000270: d148 bne.n 8000304 <__udivmoddi4+0x158> 8000272: 428b cmp r3, r1 8000274: d302 bcc.n 800027c <__udivmoddi4+0xd0> 8000276: 4282 cmp r2, r0 8000278: f200 80fb bhi.w 8000472 <__udivmoddi4+0x2c6> 800027c: 1a84 subs r4, r0, r2 800027e: eb61 0303 sbc.w r3, r1, r3 8000282: 2001 movs r0, #1 8000284: 469c mov ip, r3 8000286: 2e00 cmp r6, #0 8000288: d0e0 beq.n 800024c <__udivmoddi4+0xa0> 800028a: e9c6 4c00 strd r4, ip, [r6] 800028e: e7dd b.n 800024c <__udivmoddi4+0xa0> 8000290: b902 cbnz r2, 8000294 <__udivmoddi4+0xe8> 8000292: deff udf #255 ; 0xff 8000294: fab2 f282 clz r2, r2 8000298: 2a00 cmp r2, #0 800029a: f040 808f bne.w 80003bc <__udivmoddi4+0x210> 800029e: 2701 movs r7, #1 80002a0: 1b49 subs r1, r1, r5 80002a2: ea4f 4815 mov.w r8, r5, lsr #16 80002a6: fa1f f985 uxth.w r9, r5 80002aa: fbb1 fef8 udiv lr, r1, r8 80002ae: fb08 111e mls r1, r8, lr, r1 80002b2: fb09 f00e mul.w r0, r9, lr 80002b6: ea4f 4c14 mov.w ip, r4, lsr #16 80002ba: ea4c 4301 orr.w r3, ip, r1, lsl #16 80002be: 4298 cmp r0, r3 80002c0: d907 bls.n 80002d2 <__udivmoddi4+0x126> 80002c2: 18eb adds r3, r5, r3 80002c4: f10e 31ff add.w r1, lr, #4294967295 ; 0xffffffff 80002c8: d202 bcs.n 80002d0 <__udivmoddi4+0x124> 80002ca: 4298 cmp r0, r3 80002cc: f200 80cd bhi.w 800046a <__udivmoddi4+0x2be> 80002d0: 468e mov lr, r1 80002d2: 1a1b subs r3, r3, r0 80002d4: fbb3 f0f8 udiv r0, r3, r8 80002d8: fb08 3310 mls r3, r8, r0, r3 80002dc: fb09 f900 mul.w r9, r9, r0 80002e0: b2a4 uxth r4, r4 80002e2: ea44 4403 orr.w r4, r4, r3, lsl #16 80002e6: 45a1 cmp r9, r4 80002e8: d907 bls.n 80002fa <__udivmoddi4+0x14e> 80002ea: 192c adds r4, r5, r4 80002ec: f100 33ff add.w r3, r0, #4294967295 ; 0xffffffff 80002f0: d202 bcs.n 80002f8 <__udivmoddi4+0x14c> 80002f2: 45a1 cmp r9, r4 80002f4: f200 80b6 bhi.w 8000464 <__udivmoddi4+0x2b8> 80002f8: 4618 mov r0, r3 80002fa: eba4 0409 sub.w r4, r4, r9 80002fe: ea40 400e orr.w r0, r0, lr, lsl #16 8000302: e79e b.n 8000242 <__udivmoddi4+0x96> 8000304: f1c7 0520 rsb r5, r7, #32 8000308: 40bb lsls r3, r7 800030a: fa22 fc05 lsr.w ip, r2, r5 800030e: ea4c 0c03 orr.w ip, ip, r3 8000312: fa21 f405 lsr.w r4, r1, r5 8000316: ea4f 4e1c mov.w lr, ip, lsr #16 800031a: fbb4 f9fe udiv r9, r4, lr 800031e: fa1f f88c uxth.w r8, ip 8000322: fb0e 4419 mls r4, lr, r9, r4 8000326: fa20 f305 lsr.w r3, r0, r5 800032a: 40b9 lsls r1, r7 800032c: fb09 fa08 mul.w sl, r9, r8 8000330: 4319 orrs r1, r3 8000332: 0c0b lsrs r3, r1, #16 8000334: ea43 4404 orr.w r4, r3, r4, lsl #16 8000338: 45a2 cmp sl, r4 800033a: fa02 f207 lsl.w r2, r2, r7 800033e: fa00 f307 lsl.w r3, r0, r7 8000342: d90b bls.n 800035c <__udivmoddi4+0x1b0> 8000344: eb1c 0404 adds.w r4, ip, r4 8000348: f109 30ff add.w r0, r9, #4294967295 ; 0xffffffff 800034c: f080 8088 bcs.w 8000460 <__udivmoddi4+0x2b4> 8000350: 45a2 cmp sl, r4 8000352: f240 8085 bls.w 8000460 <__udivmoddi4+0x2b4> 8000356: f1a9 0902 sub.w r9, r9, #2 800035a: 4464 add r4, ip 800035c: eba4 040a sub.w r4, r4, sl 8000360: fbb4 f0fe udiv r0, r4, lr 8000364: fb0e 4410 mls r4, lr, r0, r4 8000368: fb00 fa08 mul.w sl, r0, r8 800036c: b289 uxth r1, r1 800036e: ea41 4404 orr.w r4, r1, r4, lsl #16 8000372: 45a2 cmp sl, r4 8000374: d908 bls.n 8000388 <__udivmoddi4+0x1dc> 8000376: eb1c 0404 adds.w r4, ip, r4 800037a: f100 31ff add.w r1, r0, #4294967295 ; 0xffffffff 800037e: d26b bcs.n 8000458 <__udivmoddi4+0x2ac> 8000380: 45a2 cmp sl, r4 8000382: d969 bls.n 8000458 <__udivmoddi4+0x2ac> 8000384: 3802 subs r0, #2 8000386: 4464 add r4, ip 8000388: ea40 4009 orr.w r0, r0, r9, lsl #16 800038c: fba0 8902 umull r8, r9, r0, r2 8000390: eba4 040a sub.w r4, r4, sl 8000394: 454c cmp r4, r9 8000396: 4641 mov r1, r8 8000398: 46ce mov lr, r9 800039a: d354 bcc.n 8000446 <__udivmoddi4+0x29a> 800039c: d051 beq.n 8000442 <__udivmoddi4+0x296> 800039e: 2e00 cmp r6, #0 80003a0: d069 beq.n 8000476 <__udivmoddi4+0x2ca> 80003a2: 1a5a subs r2, r3, r1 80003a4: eb64 040e sbc.w r4, r4, lr 80003a8: fa04 f505 lsl.w r5, r4, r5 80003ac: fa22 f307 lsr.w r3, r2, r7 80003b0: 40fc lsrs r4, r7 80003b2: 431d orrs r5, r3 80003b4: e9c6 5400 strd r5, r4, [r6] 80003b8: 2700 movs r7, #0 80003ba: e747 b.n 800024c <__udivmoddi4+0xa0> 80003bc: 4095 lsls r5, r2 80003be: f1c2 0320 rsb r3, r2, #32 80003c2: fa21 f003 lsr.w r0, r1, r3 80003c6: ea4f 4815 mov.w r8, r5, lsr #16 80003ca: fbb0 f7f8 udiv r7, r0, r8 80003ce: fa1f f985 uxth.w r9, r5 80003d2: fb08 0017 mls r0, r8, r7, r0 80003d6: fa24 f303 lsr.w r3, r4, r3 80003da: 4091 lsls r1, r2 80003dc: fb07 fc09 mul.w ip, r7, r9 80003e0: 430b orrs r3, r1 80003e2: 0c19 lsrs r1, r3, #16 80003e4: ea41 4100 orr.w r1, r1, r0, lsl #16 80003e8: 458c cmp ip, r1 80003ea: fa04 f402 lsl.w r4, r4, r2 80003ee: d907 bls.n 8000400 <__udivmoddi4+0x254> 80003f0: 1869 adds r1, r5, r1 80003f2: f107 30ff add.w r0, r7, #4294967295 ; 0xffffffff 80003f6: d231 bcs.n 800045c <__udivmoddi4+0x2b0> 80003f8: 458c cmp ip, r1 80003fa: d92f bls.n 800045c <__udivmoddi4+0x2b0> 80003fc: 3f02 subs r7, #2 80003fe: 4429 add r1, r5 8000400: eba1 010c sub.w r1, r1, ip 8000404: fbb1 f0f8 udiv r0, r1, r8 8000408: fb08 1c10 mls ip, r8, r0, r1 800040c: fb00 fe09 mul.w lr, r0, r9 8000410: b299 uxth r1, r3 8000412: ea41 410c orr.w r1, r1, ip, lsl #16 8000416: 458e cmp lr, r1 8000418: d907 bls.n 800042a <__udivmoddi4+0x27e> 800041a: 1869 adds r1, r5, r1 800041c: f100 33ff add.w r3, r0, #4294967295 ; 0xffffffff 8000420: d218 bcs.n 8000454 <__udivmoddi4+0x2a8> 8000422: 458e cmp lr, r1 8000424: d916 bls.n 8000454 <__udivmoddi4+0x2a8> 8000426: 3802 subs r0, #2 8000428: 4429 add r1, r5 800042a: eba1 010e sub.w r1, r1, lr 800042e: ea40 4707 orr.w r7, r0, r7, lsl #16 8000432: e73a b.n 80002aa <__udivmoddi4+0xfe> 8000434: 4637 mov r7, r6 8000436: 4630 mov r0, r6 8000438: e708 b.n 800024c <__udivmoddi4+0xa0> 800043a: 460f mov r7, r1 800043c: e6e6 b.n 800020c <__udivmoddi4+0x60> 800043e: 4618 mov r0, r3 8000440: e6fb b.n 800023a <__udivmoddi4+0x8e> 8000442: 4543 cmp r3, r8 8000444: d2ab bcs.n 800039e <__udivmoddi4+0x1f2> 8000446: ebb8 0102 subs.w r1, r8, r2 800044a: eb69 020c sbc.w r2, r9, ip 800044e: 3801 subs r0, #1 8000450: 4696 mov lr, r2 8000452: e7a4 b.n 800039e <__udivmoddi4+0x1f2> 8000454: 4618 mov r0, r3 8000456: e7e8 b.n 800042a <__udivmoddi4+0x27e> 8000458: 4608 mov r0, r1 800045a: e795 b.n 8000388 <__udivmoddi4+0x1dc> 800045c: 4607 mov r7, r0 800045e: e7cf b.n 8000400 <__udivmoddi4+0x254> 8000460: 4681 mov r9, r0 8000462: e77b b.n 800035c <__udivmoddi4+0x1b0> 8000464: 3802 subs r0, #2 8000466: 442c add r4, r5 8000468: e747 b.n 80002fa <__udivmoddi4+0x14e> 800046a: f1ae 0e02 sub.w lr, lr, #2 800046e: 442b add r3, r5 8000470: e72f b.n 80002d2 <__udivmoddi4+0x126> 8000472: 4638 mov r0, r7 8000474: e707 b.n 8000286 <__udivmoddi4+0xda> 8000476: 4637 mov r7, r6 8000478: e6e8 b.n 800024c <__udivmoddi4+0xa0> 800047a: bf00 nop 0800047c <__aeabi_idiv0>: 800047c: 4770 bx lr 800047e: bf00 nop 08000480
: /** * @brief The application entry point. * @retval int */ int main(void) { 8000480: b580 push {r7, lr} 8000482: af00 add r7, sp, #0 /* USER CODE END 1 */ /* MCU Configuration--------------------------------------------------------*/ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ HAL_Init(); 8000484: f000 f911 bl 80006aa /* USER CODE BEGIN Init */ /* USER CODE END Init */ /* Configure the system clock */ SystemClock_Config(); 8000488: f000 f80c bl 80004a4 /* USER CODE BEGIN SysInit */ /* USER CODE END SysInit */ /* Initialize all configured peripherals */ MX_GPIO_Init(); 800048c: f000 f852 bl 8000534 /* Infinite loop */ /* USER CODE BEGIN WHILE */ while (1) { HAL_GPIO_TogglePin(GPIOA,LED); 8000490: 2120 movs r1, #32 8000492: 4803 ldr r0, [pc, #12] ; (80004a0 ) 8000494: f000 fc24 bl 8000ce0 HAL_Delay(200); 8000498: 20c8 movs r0, #200 ; 0xc8 800049a: f000 f975 bl 8000788 HAL_GPIO_TogglePin(GPIOA,LED); 800049e: e7f7 b.n 8000490 80004a0: 40020000 .word 0x40020000 080004a4 : /** * @brief System Clock Configuration * @retval None */ void SystemClock_Config(void) { 80004a4: b580 push {r7, lr} 80004a6: b092 sub sp, #72 ; 0x48 80004a8: af00 add r7, sp, #0 RCC_OscInitTypeDef RCC_OscInitStruct = {0}; 80004aa: f107 0314 add.w r3, r7, #20 80004ae: 2234 movs r2, #52 ; 0x34 80004b0: 2100 movs r1, #0 80004b2: 4618 mov r0, r3 80004b4: f001 f9b8 bl 8001828 RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 80004b8: 463b mov r3, r7 80004ba: 2200 movs r2, #0 80004bc: 601a str r2, [r3, #0] 80004be: 605a str r2, [r3, #4] 80004c0: 609a str r2, [r3, #8] 80004c2: 60da str r2, [r3, #12] 80004c4: 611a str r2, [r3, #16] /** Configure the main internal regulator output voltage */ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); 80004c6: 4b1a ldr r3, [pc, #104] ; (8000530 ) 80004c8: 681b ldr r3, [r3, #0] 80004ca: f423 53c0 bic.w r3, r3, #6144 ; 0x1800 80004ce: 4a18 ldr r2, [pc, #96] ; (8000530 ) 80004d0: f443 6300 orr.w r3, r3, #2048 ; 0x800 80004d4: 6013 str r3, [r2, #0] /** Initializes the RCC Oscillators according to the specified parameters * in the RCC_OscInitTypeDef structure. */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI; 80004d6: 2310 movs r3, #16 80004d8: 617b str r3, [r7, #20] RCC_OscInitStruct.MSIState = RCC_MSI_ON; 80004da: 2301 movs r3, #1 80004dc: 62fb str r3, [r7, #44] ; 0x2c RCC_OscInitStruct.MSICalibrationValue = 0; 80004de: 2300 movs r3, #0 80004e0: 633b str r3, [r7, #48] ; 0x30 RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_5; 80004e2: f44f 4320 mov.w r3, #40960 ; 0xa000 80004e6: 637b str r3, [r7, #52] ; 0x34 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; 80004e8: 2300 movs r3, #0 80004ea: 63bb str r3, [r7, #56] ; 0x38 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 80004ec: f107 0314 add.w r3, r7, #20 80004f0: 4618 mov r0, r3 80004f2: f000 fc0f bl 8000d14 80004f6: 4603 mov r3, r0 80004f8: 2b00 cmp r3, #0 80004fa: d001 beq.n 8000500 { Error_Handler(); 80004fc: f000 f84a bl 8000594 } /** Initializes the CPU, AHB and APB buses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK 8000500: 230f movs r3, #15 8000502: 603b str r3, [r7, #0] |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI; 8000504: 2300 movs r3, #0 8000506: 607b str r3, [r7, #4] RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; 8000508: 2300 movs r3, #0 800050a: 60bb str r3, [r7, #8] RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; 800050c: 2300 movs r3, #0 800050e: 60fb str r3, [r7, #12] RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; 8000510: 2300 movs r3, #0 8000512: 613b str r3, [r7, #16] if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK) 8000514: 463b mov r3, r7 8000516: 2100 movs r1, #0 8000518: 4618 mov r0, r3 800051a: f000 ff2b bl 8001374 800051e: 4603 mov r3, r0 8000520: 2b00 cmp r3, #0 8000522: d001 beq.n 8000528 { Error_Handler(); 8000524: f000 f836 bl 8000594 } } 8000528: bf00 nop 800052a: 3748 adds r7, #72 ; 0x48 800052c: 46bd mov sp, r7 800052e: bd80 pop {r7, pc} 8000530: 40007000 .word 0x40007000 08000534 : * @brief GPIO Initialization Function * @param None * @retval None */ static void MX_GPIO_Init(void) { 8000534: b580 push {r7, lr} 8000536: b086 sub sp, #24 8000538: af00 add r7, sp, #0 GPIO_InitTypeDef GPIO_InitStruct = {0}; 800053a: 1d3b adds r3, r7, #4 800053c: 2200 movs r2, #0 800053e: 601a str r2, [r3, #0] 8000540: 605a str r2, [r3, #4] 8000542: 609a str r2, [r3, #8] 8000544: 60da str r2, [r3, #12] 8000546: 611a str r2, [r3, #16] /* GPIO Ports Clock Enable */ __HAL_RCC_GPIOA_CLK_ENABLE(); 8000548: 4b10 ldr r3, [pc, #64] ; (800058c ) 800054a: 69db ldr r3, [r3, #28] 800054c: 4a0f ldr r2, [pc, #60] ; (800058c ) 800054e: f043 0301 orr.w r3, r3, #1 8000552: 61d3 str r3, [r2, #28] 8000554: 4b0d ldr r3, [pc, #52] ; (800058c ) 8000556: 69db ldr r3, [r3, #28] 8000558: f003 0301 and.w r3, r3, #1 800055c: 603b str r3, [r7, #0] 800055e: 683b ldr r3, [r7, #0] /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOA, GPIO_PIN_5, GPIO_PIN_RESET); 8000560: 2200 movs r2, #0 8000562: 2120 movs r1, #32 8000564: 480a ldr r0, [pc, #40] ; (8000590 ) 8000566: f000 fba3 bl 8000cb0 /*Configure GPIO pin : PA5 */ GPIO_InitStruct.Pin = GPIO_PIN_5; 800056a: 2320 movs r3, #32 800056c: 607b str r3, [r7, #4] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 800056e: 2301 movs r3, #1 8000570: 60bb str r3, [r7, #8] GPIO_InitStruct.Pull = GPIO_NOPULL; 8000572: 2300 movs r3, #0 8000574: 60fb str r3, [r7, #12] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8000576: 2300 movs r3, #0 8000578: 613b str r3, [r7, #16] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 800057a: 1d3b adds r3, r7, #4 800057c: 4619 mov r1, r3 800057e: 4804 ldr r0, [pc, #16] ; (8000590 ) 8000580: f000 fa08 bl 8000994 } 8000584: bf00 nop 8000586: 3718 adds r7, #24 8000588: 46bd mov sp, r7 800058a: bd80 pop {r7, pc} 800058c: 40023800 .word 0x40023800 8000590: 40020000 .word 0x40020000 08000594 : /** * @brief This function is executed in case of error occurrence. * @retval None */ void Error_Handler(void) { 8000594: b480 push {r7} 8000596: af00 add r7, sp, #0 \details Disables IRQ interrupts by setting the I-bit in the CPSR. Can only be executed in Privileged modes. */ __STATIC_FORCEINLINE void __disable_irq(void) { __ASM volatile ("cpsid i" : : : "memory"); 8000598: b672 cpsid i /* USER CODE BEGIN Error_Handler_Debug */ /* User can add his own implementation to report the HAL error return state */ __disable_irq(); while (1) 800059a: e7fe b.n 800059a 0800059c : /* USER CODE END 0 */ /** * Initializes the Global MSP. */ void HAL_MspInit(void) { 800059c: b480 push {r7} 800059e: b085 sub sp, #20 80005a0: af00 add r7, sp, #0 /* USER CODE BEGIN MspInit 0 */ /* USER CODE END MspInit 0 */ __HAL_RCC_COMP_CLK_ENABLE(); 80005a2: 4b14 ldr r3, [pc, #80] ; (80005f4 ) 80005a4: 6a5b ldr r3, [r3, #36] ; 0x24 80005a6: 4a13 ldr r2, [pc, #76] ; (80005f4 ) 80005a8: f043 4300 orr.w r3, r3, #2147483648 ; 0x80000000 80005ac: 6253 str r3, [r2, #36] ; 0x24 80005ae: 4b11 ldr r3, [pc, #68] ; (80005f4 ) 80005b0: 6a5b ldr r3, [r3, #36] ; 0x24 80005b2: f003 4300 and.w r3, r3, #2147483648 ; 0x80000000 80005b6: 60fb str r3, [r7, #12] 80005b8: 68fb ldr r3, [r7, #12] __HAL_RCC_SYSCFG_CLK_ENABLE(); 80005ba: 4b0e ldr r3, [pc, #56] ; (80005f4 ) 80005bc: 6a1b ldr r3, [r3, #32] 80005be: 4a0d ldr r2, [pc, #52] ; (80005f4 ) 80005c0: f043 0301 orr.w r3, r3, #1 80005c4: 6213 str r3, [r2, #32] 80005c6: 4b0b ldr r3, [pc, #44] ; (80005f4 ) 80005c8: 6a1b ldr r3, [r3, #32] 80005ca: f003 0301 and.w r3, r3, #1 80005ce: 60bb str r3, [r7, #8] 80005d0: 68bb ldr r3, [r7, #8] __HAL_RCC_PWR_CLK_ENABLE(); 80005d2: 4b08 ldr r3, [pc, #32] ; (80005f4 ) 80005d4: 6a5b ldr r3, [r3, #36] ; 0x24 80005d6: 4a07 ldr r2, [pc, #28] ; (80005f4 ) 80005d8: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 80005dc: 6253 str r3, [r2, #36] ; 0x24 80005de: 4b05 ldr r3, [pc, #20] ; (80005f4 ) 80005e0: 6a5b ldr r3, [r3, #36] ; 0x24 80005e2: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 80005e6: 607b str r3, [r7, #4] 80005e8: 687b ldr r3, [r7, #4] /* System interrupt init*/ /* USER CODE BEGIN MspInit 1 */ /* USER CODE END MspInit 1 */ } 80005ea: bf00 nop 80005ec: 3714 adds r7, #20 80005ee: 46bd mov sp, r7 80005f0: bc80 pop {r7} 80005f2: 4770 bx lr 80005f4: 40023800 .word 0x40023800 080005f8 : /******************************************************************************/ /** * @brief This function handles Non maskable interrupt. */ void NMI_Handler(void) { 80005f8: b480 push {r7} 80005fa: af00 add r7, sp, #0 /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ /* USER CODE END NonMaskableInt_IRQn 0 */ /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ while (1) 80005fc: e7fe b.n 80005fc 080005fe : /** * @brief This function handles Hard fault interrupt. */ void HardFault_Handler(void) { 80005fe: b480 push {r7} 8000600: af00 add r7, sp, #0 /* USER CODE BEGIN HardFault_IRQn 0 */ /* USER CODE END HardFault_IRQn 0 */ while (1) 8000602: e7fe b.n 8000602 08000604 : /** * @brief This function handles Memory management fault. */ void MemManage_Handler(void) { 8000604: b480 push {r7} 8000606: af00 add r7, sp, #0 /* USER CODE BEGIN MemoryManagement_IRQn 0 */ /* USER CODE END MemoryManagement_IRQn 0 */ while (1) 8000608: e7fe b.n 8000608 0800060a : /** * @brief This function handles Pre-fetch fault, memory access fault. */ void BusFault_Handler(void) { 800060a: b480 push {r7} 800060c: af00 add r7, sp, #0 /* USER CODE BEGIN BusFault_IRQn 0 */ /* USER CODE END BusFault_IRQn 0 */ while (1) 800060e: e7fe b.n 800060e 08000610 : /** * @brief This function handles Undefined instruction or illegal state. */ void UsageFault_Handler(void) { 8000610: b480 push {r7} 8000612: af00 add r7, sp, #0 /* USER CODE BEGIN UsageFault_IRQn 0 */ /* USER CODE END UsageFault_IRQn 0 */ while (1) 8000614: e7fe b.n 8000614 08000616 : /** * @brief This function handles System service call via SWI instruction. */ void SVC_Handler(void) { 8000616: b480 push {r7} 8000618: af00 add r7, sp, #0 /* USER CODE END SVC_IRQn 0 */ /* USER CODE BEGIN SVC_IRQn 1 */ /* USER CODE END SVC_IRQn 1 */ } 800061a: bf00 nop 800061c: 46bd mov sp, r7 800061e: bc80 pop {r7} 8000620: 4770 bx lr 08000622 : /** * @brief This function handles Debug monitor. */ void DebugMon_Handler(void) { 8000622: b480 push {r7} 8000624: af00 add r7, sp, #0 /* USER CODE END DebugMonitor_IRQn 0 */ /* USER CODE BEGIN DebugMonitor_IRQn 1 */ /* USER CODE END DebugMonitor_IRQn 1 */ } 8000626: bf00 nop 8000628: 46bd mov sp, r7 800062a: bc80 pop {r7} 800062c: 4770 bx lr 0800062e : /** * @brief This function handles Pendable request for system service. */ void PendSV_Handler(void) { 800062e: b480 push {r7} 8000630: af00 add r7, sp, #0 /* USER CODE END PendSV_IRQn 0 */ /* USER CODE BEGIN PendSV_IRQn 1 */ /* USER CODE END PendSV_IRQn 1 */ } 8000632: bf00 nop 8000634: 46bd mov sp, r7 8000636: bc80 pop {r7} 8000638: 4770 bx lr 0800063a : /** * @brief This function handles System tick timer. */ void SysTick_Handler(void) { 800063a: b580 push {r7, lr} 800063c: af00 add r7, sp, #0 /* USER CODE BEGIN SysTick_IRQn 0 */ /* USER CODE END SysTick_IRQn 0 */ HAL_IncTick(); 800063e: f000 f887 bl 8000750 /* USER CODE BEGIN SysTick_IRQn 1 */ /* USER CODE END SysTick_IRQn 1 */ } 8000642: bf00 nop 8000644: bd80 pop {r7, pc} ... 08000648 : * SystemCoreClock variable. * @param None * @retval None */ void SystemInit (void) { 8000648: b480 push {r7} 800064a: af00 add r7, sp, #0 #endif /* DATA_IN_ExtSRAM */ #ifdef VECT_TAB_SRAM SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ #else SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */ 800064c: 4b03 ldr r3, [pc, #12] ; (800065c ) 800064e: f04f 6200 mov.w r2, #134217728 ; 0x8000000 8000652: 609a str r2, [r3, #8] #endif } 8000654: bf00 nop 8000656: 46bd mov sp, r7 8000658: bc80 pop {r7} 800065a: 4770 bx lr 800065c: e000ed00 .word 0xe000ed00 08000660 : .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: /* Copy the data segment initializers from flash to SRAM */ movs r1, #0 8000660: 2100 movs r1, #0 b LoopCopyDataInit 8000662: e003 b.n 800066c 08000664 : CopyDataInit: ldr r3, =_sidata 8000664: 4b0b ldr r3, [pc, #44] ; (8000694 ) ldr r3, [r3, r1] 8000666: 585b ldr r3, [r3, r1] str r3, [r0, r1] 8000668: 5043 str r3, [r0, r1] adds r1, r1, #4 800066a: 3104 adds r1, #4 0800066c : LoopCopyDataInit: ldr r0, =_sdata 800066c: 480a ldr r0, [pc, #40] ; (8000698 ) ldr r3, =_edata 800066e: 4b0b ldr r3, [pc, #44] ; (800069c ) adds r2, r0, r1 8000670: 1842 adds r2, r0, r1 cmp r2, r3 8000672: 429a cmp r2, r3 bcc CopyDataInit 8000674: d3f6 bcc.n 8000664 ldr r2, =_sbss 8000676: 4a0a ldr r2, [pc, #40] ; (80006a0 ) b LoopFillZerobss 8000678: e002 b.n 8000680 0800067a : /* Zero fill the bss segment. */ FillZerobss: movs r3, #0 800067a: 2300 movs r3, #0 str r3, [r2], #4 800067c: f842 3b04 str.w r3, [r2], #4 08000680 : LoopFillZerobss: ldr r3, = _ebss 8000680: 4b08 ldr r3, [pc, #32] ; (80006a4 ) cmp r2, r3 8000682: 429a cmp r2, r3 bcc FillZerobss 8000684: d3f9 bcc.n 800067a /* Call the clock system intitialization function.*/ bl SystemInit 8000686: f7ff ffdf bl 8000648 /* Call static constructors */ bl __libc_init_array 800068a: f001 f8a9 bl 80017e0 <__libc_init_array> /* Call the application's entry point.*/ bl main 800068e: f7ff fef7 bl 8000480
bx lr 8000692: 4770 bx lr ldr r3, =_sidata 8000694: 0800187c .word 0x0800187c ldr r0, =_sdata 8000698: 20000000 .word 0x20000000 ldr r3, =_edata 800069c: 2000000c .word 0x2000000c ldr r2, =_sbss 80006a0: 2000000c .word 0x2000000c ldr r3, = _ebss 80006a4: 2000002c .word 0x2000002c 080006a8 : * @retval : None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop 80006a8: e7fe b.n 80006a8 080006aa : * In the default implementation,Systick is used as source of time base. * the tick variable is incremented each 1ms in its ISR. * @retval HAL status */ HAL_StatusTypeDef HAL_Init(void) { 80006aa: b580 push {r7, lr} 80006ac: b082 sub sp, #8 80006ae: af00 add r7, sp, #0 HAL_StatusTypeDef status = HAL_OK; 80006b0: 2300 movs r3, #0 80006b2: 71fb strb r3, [r7, #7] #if (PREFETCH_ENABLE != 0) __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); #endif /* PREFETCH_ENABLE */ /* Set Interrupt Group Priority */ HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); 80006b4: 2003 movs r0, #3 80006b6: f000 f939 bl 800092c /* Use systick as time base source and configure 1ms tick (default clock after Reset is MSI) */ if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK) 80006ba: 2000 movs r0, #0 80006bc: f000 f80e bl 80006dc 80006c0: 4603 mov r3, r0 80006c2: 2b00 cmp r3, #0 80006c4: d002 beq.n 80006cc { status = HAL_ERROR; 80006c6: 2301 movs r3, #1 80006c8: 71fb strb r3, [r7, #7] 80006ca: e001 b.n 80006d0 } else { /* Init the low level hardware */ HAL_MspInit(); 80006cc: f7ff ff66 bl 800059c } /* Return function status */ return status; 80006d0: 79fb ldrb r3, [r7, #7] } 80006d2: 4618 mov r0, r3 80006d4: 3708 adds r7, #8 80006d6: 46bd mov sp, r7 80006d8: bd80 pop {r7, pc} ... 080006dc : * implementation in user file. * @param TickPriority Tick interrupt priority. * @retval HAL status */ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { 80006dc: b580 push {r7, lr} 80006de: b084 sub sp, #16 80006e0: af00 add r7, sp, #0 80006e2: 6078 str r0, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 80006e4: 2300 movs r3, #0 80006e6: 73fb strb r3, [r7, #15] if (uwTickFreq != 0U) 80006e8: 4b16 ldr r3, [pc, #88] ; (8000744 ) 80006ea: 681b ldr r3, [r3, #0] 80006ec: 2b00 cmp r3, #0 80006ee: d022 beq.n 8000736 { /*Configure the SysTick to have interrupt in 1ms time basis*/ if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) == 0U) 80006f0: 4b15 ldr r3, [pc, #84] ; (8000748 ) 80006f2: 681a ldr r2, [r3, #0] 80006f4: 4b13 ldr r3, [pc, #76] ; (8000744 ) 80006f6: 681b ldr r3, [r3, #0] 80006f8: f44f 717a mov.w r1, #1000 ; 0x3e8 80006fc: fbb1 f3f3 udiv r3, r1, r3 8000700: fbb2 f3f3 udiv r3, r2, r3 8000704: 4618 mov r0, r3 8000706: f000 f938 bl 800097a 800070a: 4603 mov r3, r0 800070c: 2b00 cmp r3, #0 800070e: d10f bne.n 8000730 { /* Configure the SysTick IRQ priority */ if (TickPriority < (1UL << __NVIC_PRIO_BITS)) 8000710: 687b ldr r3, [r7, #4] 8000712: 2b0f cmp r3, #15 8000714: d809 bhi.n 800072a { HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); 8000716: 2200 movs r2, #0 8000718: 6879 ldr r1, [r7, #4] 800071a: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff 800071e: f000 f910 bl 8000942 uwTickPrio = TickPriority; 8000722: 4a0a ldr r2, [pc, #40] ; (800074c ) 8000724: 687b ldr r3, [r7, #4] 8000726: 6013 str r3, [r2, #0] 8000728: e007 b.n 800073a } else { status = HAL_ERROR; 800072a: 2301 movs r3, #1 800072c: 73fb strb r3, [r7, #15] 800072e: e004 b.n 800073a } } else { status = HAL_ERROR; 8000730: 2301 movs r3, #1 8000732: 73fb strb r3, [r7, #15] 8000734: e001 b.n 800073a } } else { status = HAL_ERROR; 8000736: 2301 movs r3, #1 8000738: 73fb strb r3, [r7, #15] } /* Return function status */ return status; 800073a: 7bfb ldrb r3, [r7, #15] } 800073c: 4618 mov r0, r3 800073e: 3710 adds r7, #16 8000740: 46bd mov sp, r7 8000742: bd80 pop {r7, pc} 8000744: 20000008 .word 0x20000008 8000748: 20000000 .word 0x20000000 800074c: 20000004 .word 0x20000004 08000750 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval None */ __weak void HAL_IncTick(void) { 8000750: b480 push {r7} 8000752: af00 add r7, sp, #0 uwTick += uwTickFreq; 8000754: 4b05 ldr r3, [pc, #20] ; (800076c ) 8000756: 681a ldr r2, [r3, #0] 8000758: 4b05 ldr r3, [pc, #20] ; (8000770 ) 800075a: 681b ldr r3, [r3, #0] 800075c: 4413 add r3, r2 800075e: 4a03 ldr r2, [pc, #12] ; (800076c ) 8000760: 6013 str r3, [r2, #0] } 8000762: bf00 nop 8000764: 46bd mov sp, r7 8000766: bc80 pop {r7} 8000768: 4770 bx lr 800076a: bf00 nop 800076c: 20000028 .word 0x20000028 8000770: 20000008 .word 0x20000008 08000774 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval tick value */ __weak uint32_t HAL_GetTick(void) { 8000774: b480 push {r7} 8000776: af00 add r7, sp, #0 return uwTick; 8000778: 4b02 ldr r3, [pc, #8] ; (8000784 ) 800077a: 681b ldr r3, [r3, #0] } 800077c: 4618 mov r0, r3 800077e: 46bd mov sp, r7 8000780: bc80 pop {r7} 8000782: 4770 bx lr 8000784: 20000028 .word 0x20000028 08000788 : * implementations in user file. * @param Delay specifies the delay time length, in milliseconds. * @retval None */ __weak void HAL_Delay(uint32_t Delay) { 8000788: b580 push {r7, lr} 800078a: b084 sub sp, #16 800078c: af00 add r7, sp, #0 800078e: 6078 str r0, [r7, #4] uint32_t tickstart = HAL_GetTick(); 8000790: f7ff fff0 bl 8000774 8000794: 60b8 str r0, [r7, #8] uint32_t wait = Delay; 8000796: 687b ldr r3, [r7, #4] 8000798: 60fb str r3, [r7, #12] /* Add a period to guaranty minimum wait */ if (wait < HAL_MAX_DELAY) 800079a: 68fb ldr r3, [r7, #12] 800079c: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff 80007a0: d004 beq.n 80007ac { wait += (uint32_t)(uwTickFreq); 80007a2: 4b09 ldr r3, [pc, #36] ; (80007c8 ) 80007a4: 681b ldr r3, [r3, #0] 80007a6: 68fa ldr r2, [r7, #12] 80007a8: 4413 add r3, r2 80007aa: 60fb str r3, [r7, #12] } while((HAL_GetTick() - tickstart) < wait) 80007ac: bf00 nop 80007ae: f7ff ffe1 bl 8000774 80007b2: 4602 mov r2, r0 80007b4: 68bb ldr r3, [r7, #8] 80007b6: 1ad3 subs r3, r2, r3 80007b8: 68fa ldr r2, [r7, #12] 80007ba: 429a cmp r2, r3 80007bc: d8f7 bhi.n 80007ae { } } 80007be: bf00 nop 80007c0: 3710 adds r7, #16 80007c2: 46bd mov sp, r7 80007c4: bd80 pop {r7, pc} 80007c6: bf00 nop 80007c8: 20000008 .word 0x20000008 080007cc <__NVIC_SetPriorityGrouping>: In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Priority grouping field. */ __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { 80007cc: b480 push {r7} 80007ce: b085 sub sp, #20 80007d0: af00 add r7, sp, #0 80007d2: 6078 str r0, [r7, #4] uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 80007d4: 687b ldr r3, [r7, #4] 80007d6: f003 0307 and.w r3, r3, #7 80007da: 60fb str r3, [r7, #12] reg_value = SCB->AIRCR; /* read old register configuration */ 80007dc: 4b0c ldr r3, [pc, #48] ; (8000810 <__NVIC_SetPriorityGrouping+0x44>) 80007de: 68db ldr r3, [r3, #12] 80007e0: 60bb str r3, [r7, #8] reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ 80007e2: 68ba ldr r2, [r7, #8] 80007e4: f64f 03ff movw r3, #63743 ; 0xf8ff 80007e8: 4013 ands r3, r2 80007ea: 60bb str r3, [r7, #8] reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ 80007ec: 68fb ldr r3, [r7, #12] 80007ee: 021a lsls r2, r3, #8 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 80007f0: 68bb ldr r3, [r7, #8] 80007f2: 4313 orrs r3, r2 reg_value = (reg_value | 80007f4: f043 63bf orr.w r3, r3, #100139008 ; 0x5f80000 80007f8: f443 3300 orr.w r3, r3, #131072 ; 0x20000 80007fc: 60bb str r3, [r7, #8] SCB->AIRCR = reg_value; 80007fe: 4a04 ldr r2, [pc, #16] ; (8000810 <__NVIC_SetPriorityGrouping+0x44>) 8000800: 68bb ldr r3, [r7, #8] 8000802: 60d3 str r3, [r2, #12] } 8000804: bf00 nop 8000806: 3714 adds r7, #20 8000808: 46bd mov sp, r7 800080a: bc80 pop {r7} 800080c: 4770 bx lr 800080e: bf00 nop 8000810: e000ed00 .word 0xe000ed00 08000814 <__NVIC_GetPriorityGrouping>: \brief Get Priority Grouping \details Reads the priority grouping field from the NVIC Interrupt Controller. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) { 8000814: b480 push {r7} 8000816: af00 add r7, sp, #0 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); 8000818: 4b04 ldr r3, [pc, #16] ; (800082c <__NVIC_GetPriorityGrouping+0x18>) 800081a: 68db ldr r3, [r3, #12] 800081c: 0a1b lsrs r3, r3, #8 800081e: f003 0307 and.w r3, r3, #7 } 8000822: 4618 mov r0, r3 8000824: 46bd mov sp, r7 8000826: bc80 pop {r7} 8000828: 4770 bx lr 800082a: bf00 nop 800082c: e000ed00 .word 0xe000ed00 08000830 <__NVIC_SetPriority>: \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { 8000830: b480 push {r7} 8000832: b083 sub sp, #12 8000834: af00 add r7, sp, #0 8000836: 4603 mov r3, r0 8000838: 6039 str r1, [r7, #0] 800083a: 71fb strb r3, [r7, #7] if ((int32_t)(IRQn) >= 0) 800083c: f997 3007 ldrsb.w r3, [r7, #7] 8000840: 2b00 cmp r3, #0 8000842: db0a blt.n 800085a <__NVIC_SetPriority+0x2a> { NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 8000844: 683b ldr r3, [r7, #0] 8000846: b2da uxtb r2, r3 8000848: 490c ldr r1, [pc, #48] ; (800087c <__NVIC_SetPriority+0x4c>) 800084a: f997 3007 ldrsb.w r3, [r7, #7] 800084e: 0112 lsls r2, r2, #4 8000850: b2d2 uxtb r2, r2 8000852: 440b add r3, r1 8000854: f883 2300 strb.w r2, [r3, #768] ; 0x300 } else { SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } 8000858: e00a b.n 8000870 <__NVIC_SetPriority+0x40> SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 800085a: 683b ldr r3, [r7, #0] 800085c: b2da uxtb r2, r3 800085e: 4908 ldr r1, [pc, #32] ; (8000880 <__NVIC_SetPriority+0x50>) 8000860: 79fb ldrb r3, [r7, #7] 8000862: f003 030f and.w r3, r3, #15 8000866: 3b04 subs r3, #4 8000868: 0112 lsls r2, r2, #4 800086a: b2d2 uxtb r2, r2 800086c: 440b add r3, r1 800086e: 761a strb r2, [r3, #24] } 8000870: bf00 nop 8000872: 370c adds r7, #12 8000874: 46bd mov sp, r7 8000876: bc80 pop {r7} 8000878: 4770 bx lr 800087a: bf00 nop 800087c: e000e100 .word 0xe000e100 8000880: e000ed00 .word 0xe000ed00 08000884 : \param [in] PreemptPriority Preemptive priority value (starting from 0). \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { 8000884: b480 push {r7} 8000886: b089 sub sp, #36 ; 0x24 8000888: af00 add r7, sp, #0 800088a: 60f8 str r0, [r7, #12] 800088c: 60b9 str r1, [r7, #8] 800088e: 607a str r2, [r7, #4] uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 8000890: 68fb ldr r3, [r7, #12] 8000892: f003 0307 and.w r3, r3, #7 8000896: 61fb str r3, [r7, #28] uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); 8000898: 69fb ldr r3, [r7, #28] 800089a: f1c3 0307 rsb r3, r3, #7 800089e: 2b04 cmp r3, #4 80008a0: bf28 it cs 80008a2: 2304 movcs r3, #4 80008a4: 61bb str r3, [r7, #24] SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 80008a6: 69fb ldr r3, [r7, #28] 80008a8: 3304 adds r3, #4 80008aa: 2b06 cmp r3, #6 80008ac: d902 bls.n 80008b4 80008ae: 69fb ldr r3, [r7, #28] 80008b0: 3b03 subs r3, #3 80008b2: e000 b.n 80008b6 80008b4: 2300 movs r3, #0 80008b6: 617b str r3, [r7, #20] return ( ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 80008b8: f04f 32ff mov.w r2, #4294967295 ; 0xffffffff 80008bc: 69bb ldr r3, [r7, #24] 80008be: fa02 f303 lsl.w r3, r2, r3 80008c2: 43da mvns r2, r3 80008c4: 68bb ldr r3, [r7, #8] 80008c6: 401a ands r2, r3 80008c8: 697b ldr r3, [r7, #20] 80008ca: 409a lsls r2, r3 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) 80008cc: f04f 31ff mov.w r1, #4294967295 ; 0xffffffff 80008d0: 697b ldr r3, [r7, #20] 80008d2: fa01 f303 lsl.w r3, r1, r3 80008d6: 43d9 mvns r1, r3 80008d8: 687b ldr r3, [r7, #4] 80008da: 400b ands r3, r1 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 80008dc: 4313 orrs r3, r2 ); } 80008de: 4618 mov r0, r3 80008e0: 3724 adds r7, #36 ; 0x24 80008e2: 46bd mov sp, r7 80008e4: bc80 pop {r7} 80008e6: 4770 bx lr 080008e8 : \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { 80008e8: b580 push {r7, lr} 80008ea: b082 sub sp, #8 80008ec: af00 add r7, sp, #0 80008ee: 6078 str r0, [r7, #4] if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) 80008f0: 687b ldr r3, [r7, #4] 80008f2: 3b01 subs r3, #1 80008f4: f1b3 7f80 cmp.w r3, #16777216 ; 0x1000000 80008f8: d301 bcc.n 80008fe { return (1UL); /* Reload value impossible */ 80008fa: 2301 movs r3, #1 80008fc: e00f b.n 800091e } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ 80008fe: 4a0a ldr r2, [pc, #40] ; (8000928 ) 8000900: 687b ldr r3, [r7, #4] 8000902: 3b01 subs r3, #1 8000904: 6053 str r3, [r2, #4] NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ 8000906: 210f movs r1, #15 8000908: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff 800090c: f7ff ff90 bl 8000830 <__NVIC_SetPriority> SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ 8000910: 4b05 ldr r3, [pc, #20] ; (8000928 ) 8000912: 2200 movs r2, #0 8000914: 609a str r2, [r3, #8] SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 8000916: 4b04 ldr r3, [pc, #16] ; (8000928 ) 8000918: 2207 movs r2, #7 800091a: 601a str r2, [r3, #0] SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ 800091c: 2300 movs r3, #0 } 800091e: 4618 mov r0, r3 8000920: 3708 adds r7, #8 8000922: 46bd mov sp, r7 8000924: bd80 pop {r7, pc} 8000926: bf00 nop 8000928: e000e010 .word 0xe000e010 0800092c : * @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible. * The pending IRQ priority will be managed only by the subpriority. * @retval None */ void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { 800092c: b580 push {r7, lr} 800092e: b082 sub sp, #8 8000930: af00 add r7, sp, #0 8000932: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ NVIC_SetPriorityGrouping(PriorityGroup); 8000934: 6878 ldr r0, [r7, #4] 8000936: f7ff ff49 bl 80007cc <__NVIC_SetPriorityGrouping> } 800093a: bf00 nop 800093c: 3708 adds r7, #8 800093e: 46bd mov sp, r7 8000940: bd80 pop {r7, pc} 08000942 : * This parameter can be a value between 0 and 15 * A lower priority value indicates a higher priority. * @retval None */ void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) { 8000942: b580 push {r7, lr} 8000944: b086 sub sp, #24 8000946: af00 add r7, sp, #0 8000948: 4603 mov r3, r0 800094a: 60b9 str r1, [r7, #8] 800094c: 607a str r2, [r7, #4] 800094e: 73fb strb r3, [r7, #15] uint32_t prioritygroup = 0x00; 8000950: 2300 movs r3, #0 8000952: 617b str r3, [r7, #20] /* Check the parameters */ assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); prioritygroup = NVIC_GetPriorityGrouping(); 8000954: f7ff ff5e bl 8000814 <__NVIC_GetPriorityGrouping> 8000958: 6178 str r0, [r7, #20] NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); 800095a: 687a ldr r2, [r7, #4] 800095c: 68b9 ldr r1, [r7, #8] 800095e: 6978 ldr r0, [r7, #20] 8000960: f7ff ff90 bl 8000884 8000964: 4602 mov r2, r0 8000966: f997 300f ldrsb.w r3, [r7, #15] 800096a: 4611 mov r1, r2 800096c: 4618 mov r0, r3 800096e: f7ff ff5f bl 8000830 <__NVIC_SetPriority> } 8000972: bf00 nop 8000974: 3718 adds r7, #24 8000976: 46bd mov sp, r7 8000978: bd80 pop {r7, pc} 0800097a : * @param TicksNumb Specifies the ticks Number of ticks between two interrupts. * @retval status: - 0 Function succeeded. * - 1 Function failed. */ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) { 800097a: b580 push {r7, lr} 800097c: b082 sub sp, #8 800097e: af00 add r7, sp, #0 8000980: 6078 str r0, [r7, #4] return SysTick_Config(TicksNumb); 8000982: 6878 ldr r0, [r7, #4] 8000984: f7ff ffb0 bl 80008e8 8000988: 4603 mov r3, r0 } 800098a: 4618 mov r0, r3 800098c: 3708 adds r7, #8 800098e: 46bd mov sp, r7 8000990: bd80 pop {r7, pc} ... 08000994 : * @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains * the configuration information for the specified GPIO peripheral. * @retval None */ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) { 8000994: b480 push {r7} 8000996: b087 sub sp, #28 8000998: af00 add r7, sp, #0 800099a: 6078 str r0, [r7, #4] 800099c: 6039 str r1, [r7, #0] uint32_t position = 0x00; 800099e: 2300 movs r3, #0 80009a0: 617b str r3, [r7, #20] uint32_t iocurrent = 0x00; 80009a2: 2300 movs r3, #0 80009a4: 60fb str r3, [r7, #12] uint32_t temp = 0x00; 80009a6: 2300 movs r3, #0 80009a8: 613b str r3, [r7, #16] assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); /* Configure the port pins */ while (((GPIO_Init->Pin) >> position) != 0) 80009aa: e160 b.n 8000c6e { /* Get current io position */ iocurrent = (GPIO_Init->Pin) & (1U << position); 80009ac: 683b ldr r3, [r7, #0] 80009ae: 681a ldr r2, [r3, #0] 80009b0: 2101 movs r1, #1 80009b2: 697b ldr r3, [r7, #20] 80009b4: fa01 f303 lsl.w r3, r1, r3 80009b8: 4013 ands r3, r2 80009ba: 60fb str r3, [r7, #12] if (iocurrent) 80009bc: 68fb ldr r3, [r7, #12] 80009be: 2b00 cmp r3, #0 80009c0: f000 8152 beq.w 8000c68 { /*--------------------- GPIO Mode Configuration ------------------------*/ /* In case of Output or Alternate function mode selection */ if ((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) || 80009c4: 683b ldr r3, [r7, #0] 80009c6: 685b ldr r3, [r3, #4] 80009c8: 2b01 cmp r3, #1 80009ca: d00b beq.n 80009e4 80009cc: 683b ldr r3, [r7, #0] 80009ce: 685b ldr r3, [r3, #4] 80009d0: 2b02 cmp r3, #2 80009d2: d007 beq.n 80009e4 (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD)) 80009d4: 683b ldr r3, [r7, #0] 80009d6: 685b ldr r3, [r3, #4] if ((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) || 80009d8: 2b11 cmp r3, #17 80009da: d003 beq.n 80009e4 (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD)) 80009dc: 683b ldr r3, [r7, #0] 80009de: 685b ldr r3, [r3, #4] 80009e0: 2b12 cmp r3, #18 80009e2: d130 bne.n 8000a46 { /* Check the Speed parameter */ assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); /* Configure the IO Speed */ temp = GPIOx->OSPEEDR; 80009e4: 687b ldr r3, [r7, #4] 80009e6: 689b ldr r3, [r3, #8] 80009e8: 613b str r3, [r7, #16] CLEAR_BIT(temp, GPIO_OSPEEDER_OSPEEDR0 << (position * 2)); 80009ea: 697b ldr r3, [r7, #20] 80009ec: 005b lsls r3, r3, #1 80009ee: 2203 movs r2, #3 80009f0: fa02 f303 lsl.w r3, r2, r3 80009f4: 43db mvns r3, r3 80009f6: 693a ldr r2, [r7, #16] 80009f8: 4013 ands r3, r2 80009fa: 613b str r3, [r7, #16] SET_BIT(temp, GPIO_Init->Speed << (position * 2)); 80009fc: 683b ldr r3, [r7, #0] 80009fe: 68da ldr r2, [r3, #12] 8000a00: 697b ldr r3, [r7, #20] 8000a02: 005b lsls r3, r3, #1 8000a04: fa02 f303 lsl.w r3, r2, r3 8000a08: 693a ldr r2, [r7, #16] 8000a0a: 4313 orrs r3, r2 8000a0c: 613b str r3, [r7, #16] GPIOx->OSPEEDR = temp; 8000a0e: 687b ldr r3, [r7, #4] 8000a10: 693a ldr r2, [r7, #16] 8000a12: 609a str r2, [r3, #8] /* Configure the IO Output Type */ temp = GPIOx->OTYPER; 8000a14: 687b ldr r3, [r7, #4] 8000a16: 685b ldr r3, [r3, #4] 8000a18: 613b str r3, [r7, #16] CLEAR_BIT(temp, GPIO_OTYPER_OT_0 << position) ; 8000a1a: 2201 movs r2, #1 8000a1c: 697b ldr r3, [r7, #20] 8000a1e: fa02 f303 lsl.w r3, r2, r3 8000a22: 43db mvns r3, r3 8000a24: 693a ldr r2, [r7, #16] 8000a26: 4013 ands r3, r2 8000a28: 613b str r3, [r7, #16] SET_BIT(temp, ((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4) << position); 8000a2a: 683b ldr r3, [r7, #0] 8000a2c: 685b ldr r3, [r3, #4] 8000a2e: 091b lsrs r3, r3, #4 8000a30: f003 0201 and.w r2, r3, #1 8000a34: 697b ldr r3, [r7, #20] 8000a36: fa02 f303 lsl.w r3, r2, r3 8000a3a: 693a ldr r2, [r7, #16] 8000a3c: 4313 orrs r3, r2 8000a3e: 613b str r3, [r7, #16] GPIOx->OTYPER = temp; 8000a40: 687b ldr r3, [r7, #4] 8000a42: 693a ldr r2, [r7, #16] 8000a44: 605a str r2, [r3, #4] } /* Activate the Pull-up or Pull down resistor for the current IO */ temp = GPIOx->PUPDR; 8000a46: 687b ldr r3, [r7, #4] 8000a48: 68db ldr r3, [r3, #12] 8000a4a: 613b str r3, [r7, #16] CLEAR_BIT(temp, GPIO_PUPDR_PUPDR0 << (position * 2)); 8000a4c: 697b ldr r3, [r7, #20] 8000a4e: 005b lsls r3, r3, #1 8000a50: 2203 movs r2, #3 8000a52: fa02 f303 lsl.w r3, r2, r3 8000a56: 43db mvns r3, r3 8000a58: 693a ldr r2, [r7, #16] 8000a5a: 4013 ands r3, r2 8000a5c: 613b str r3, [r7, #16] SET_BIT(temp, (GPIO_Init->Pull) << (position * 2)); 8000a5e: 683b ldr r3, [r7, #0] 8000a60: 689a ldr r2, [r3, #8] 8000a62: 697b ldr r3, [r7, #20] 8000a64: 005b lsls r3, r3, #1 8000a66: fa02 f303 lsl.w r3, r2, r3 8000a6a: 693a ldr r2, [r7, #16] 8000a6c: 4313 orrs r3, r2 8000a6e: 613b str r3, [r7, #16] GPIOx->PUPDR = temp; 8000a70: 687b ldr r3, [r7, #4] 8000a72: 693a ldr r2, [r7, #16] 8000a74: 60da str r2, [r3, #12] /* In case of Alternate function mode selection */ if ((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD)) 8000a76: 683b ldr r3, [r7, #0] 8000a78: 685b ldr r3, [r3, #4] 8000a7a: 2b02 cmp r3, #2 8000a7c: d003 beq.n 8000a86 8000a7e: 683b ldr r3, [r7, #0] 8000a80: 685b ldr r3, [r3, #4] 8000a82: 2b12 cmp r3, #18 8000a84: d123 bne.n 8000ace assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); /* Configure Alternate function mapped with the current IO */ /* Identify AFRL or AFRH register based on IO position*/ temp = GPIOx->AFR[position >> 3]; 8000a86: 697b ldr r3, [r7, #20] 8000a88: 08da lsrs r2, r3, #3 8000a8a: 687b ldr r3, [r7, #4] 8000a8c: 3208 adds r2, #8 8000a8e: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8000a92: 613b str r3, [r7, #16] CLEAR_BIT(temp, 0xFU << ((uint32_t)(position & 0x07U) * 4)); 8000a94: 697b ldr r3, [r7, #20] 8000a96: f003 0307 and.w r3, r3, #7 8000a9a: 009b lsls r3, r3, #2 8000a9c: 220f movs r2, #15 8000a9e: fa02 f303 lsl.w r3, r2, r3 8000aa2: 43db mvns r3, r3 8000aa4: 693a ldr r2, [r7, #16] 8000aa6: 4013 ands r3, r2 8000aa8: 613b str r3, [r7, #16] SET_BIT(temp, (uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & 0x07U) * 4)); 8000aaa: 683b ldr r3, [r7, #0] 8000aac: 691a ldr r2, [r3, #16] 8000aae: 697b ldr r3, [r7, #20] 8000ab0: f003 0307 and.w r3, r3, #7 8000ab4: 009b lsls r3, r3, #2 8000ab6: fa02 f303 lsl.w r3, r2, r3 8000aba: 693a ldr r2, [r7, #16] 8000abc: 4313 orrs r3, r2 8000abe: 613b str r3, [r7, #16] GPIOx->AFR[position >> 3] = temp; 8000ac0: 697b ldr r3, [r7, #20] 8000ac2: 08da lsrs r2, r3, #3 8000ac4: 687b ldr r3, [r7, #4] 8000ac6: 3208 adds r2, #8 8000ac8: 6939 ldr r1, [r7, #16] 8000aca: f843 1022 str.w r1, [r3, r2, lsl #2] } /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ temp = GPIOx->MODER; 8000ace: 687b ldr r3, [r7, #4] 8000ad0: 681b ldr r3, [r3, #0] 8000ad2: 613b str r3, [r7, #16] CLEAR_BIT(temp, GPIO_MODER_MODER0 << (position * 2)); 8000ad4: 697b ldr r3, [r7, #20] 8000ad6: 005b lsls r3, r3, #1 8000ad8: 2203 movs r2, #3 8000ada: fa02 f303 lsl.w r3, r2, r3 8000ade: 43db mvns r3, r3 8000ae0: 693a ldr r2, [r7, #16] 8000ae2: 4013 ands r3, r2 8000ae4: 613b str r3, [r7, #16] SET_BIT(temp, (GPIO_Init->Mode & GPIO_MODE) << (position * 2)); 8000ae6: 683b ldr r3, [r7, #0] 8000ae8: 685b ldr r3, [r3, #4] 8000aea: f003 0203 and.w r2, r3, #3 8000aee: 697b ldr r3, [r7, #20] 8000af0: 005b lsls r3, r3, #1 8000af2: fa02 f303 lsl.w r3, r2, r3 8000af6: 693a ldr r2, [r7, #16] 8000af8: 4313 orrs r3, r2 8000afa: 613b str r3, [r7, #16] GPIOx->MODER = temp; 8000afc: 687b ldr r3, [r7, #4] 8000afe: 693a ldr r2, [r7, #16] 8000b00: 601a str r2, [r3, #0] /*--------------------- EXTI Mode Configuration ------------------------*/ /* Configure the External Interrupt or event for the current IO */ if ((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE) 8000b02: 683b ldr r3, [r7, #0] 8000b04: 685b ldr r3, [r3, #4] 8000b06: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 8000b0a: 2b00 cmp r3, #0 8000b0c: f000 80ac beq.w 8000c68 { /* Enable SYSCFG Clock */ __HAL_RCC_SYSCFG_CLK_ENABLE(); 8000b10: 4b5d ldr r3, [pc, #372] ; (8000c88 ) 8000b12: 6a1b ldr r3, [r3, #32] 8000b14: 4a5c ldr r2, [pc, #368] ; (8000c88 ) 8000b16: f043 0301 orr.w r3, r3, #1 8000b1a: 6213 str r3, [r2, #32] 8000b1c: 4b5a ldr r3, [pc, #360] ; (8000c88 ) 8000b1e: 6a1b ldr r3, [r3, #32] 8000b20: f003 0301 and.w r3, r3, #1 8000b24: 60bb str r3, [r7, #8] 8000b26: 68bb ldr r3, [r7, #8] temp = SYSCFG->EXTICR[position >> 2]; 8000b28: 4a58 ldr r2, [pc, #352] ; (8000c8c ) 8000b2a: 697b ldr r3, [r7, #20] 8000b2c: 089b lsrs r3, r3, #2 8000b2e: 3302 adds r3, #2 8000b30: f852 3023 ldr.w r3, [r2, r3, lsl #2] 8000b34: 613b str r3, [r7, #16] CLEAR_BIT(temp, (0x0FU) << (4 * (position & 0x03))); 8000b36: 697b ldr r3, [r7, #20] 8000b38: f003 0303 and.w r3, r3, #3 8000b3c: 009b lsls r3, r3, #2 8000b3e: 220f movs r2, #15 8000b40: fa02 f303 lsl.w r3, r2, r3 8000b44: 43db mvns r3, r3 8000b46: 693a ldr r2, [r7, #16] 8000b48: 4013 ands r3, r2 8000b4a: 613b str r3, [r7, #16] SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03))); 8000b4c: 687b ldr r3, [r7, #4] 8000b4e: 4a50 ldr r2, [pc, #320] ; (8000c90 ) 8000b50: 4293 cmp r3, r2 8000b52: d025 beq.n 8000ba0 8000b54: 687b ldr r3, [r7, #4] 8000b56: 4a4f ldr r2, [pc, #316] ; (8000c94 ) 8000b58: 4293 cmp r3, r2 8000b5a: d01f beq.n 8000b9c 8000b5c: 687b ldr r3, [r7, #4] 8000b5e: 4a4e ldr r2, [pc, #312] ; (8000c98 ) 8000b60: 4293 cmp r3, r2 8000b62: d019 beq.n 8000b98 8000b64: 687b ldr r3, [r7, #4] 8000b66: 4a4d ldr r2, [pc, #308] ; (8000c9c ) 8000b68: 4293 cmp r3, r2 8000b6a: d013 beq.n 8000b94 8000b6c: 687b ldr r3, [r7, #4] 8000b6e: 4a4c ldr r2, [pc, #304] ; (8000ca0 ) 8000b70: 4293 cmp r3, r2 8000b72: d00d beq.n 8000b90 8000b74: 687b ldr r3, [r7, #4] 8000b76: 4a4b ldr r2, [pc, #300] ; (8000ca4 ) 8000b78: 4293 cmp r3, r2 8000b7a: d007 beq.n 8000b8c 8000b7c: 687b ldr r3, [r7, #4] 8000b7e: 4a4a ldr r2, [pc, #296] ; (8000ca8 ) 8000b80: 4293 cmp r3, r2 8000b82: d101 bne.n 8000b88 8000b84: 2306 movs r3, #6 8000b86: e00c b.n 8000ba2 8000b88: 2307 movs r3, #7 8000b8a: e00a b.n 8000ba2 8000b8c: 2305 movs r3, #5 8000b8e: e008 b.n 8000ba2 8000b90: 2304 movs r3, #4 8000b92: e006 b.n 8000ba2 8000b94: 2303 movs r3, #3 8000b96: e004 b.n 8000ba2 8000b98: 2302 movs r3, #2 8000b9a: e002 b.n 8000ba2 8000b9c: 2301 movs r3, #1 8000b9e: e000 b.n 8000ba2 8000ba0: 2300 movs r3, #0 8000ba2: 697a ldr r2, [r7, #20] 8000ba4: f002 0203 and.w r2, r2, #3 8000ba8: 0092 lsls r2, r2, #2 8000baa: 4093 lsls r3, r2 8000bac: 693a ldr r2, [r7, #16] 8000bae: 4313 orrs r3, r2 8000bb0: 613b str r3, [r7, #16] SYSCFG->EXTICR[position >> 2] = temp; 8000bb2: 4936 ldr r1, [pc, #216] ; (8000c8c ) 8000bb4: 697b ldr r3, [r7, #20] 8000bb6: 089b lsrs r3, r3, #2 8000bb8: 3302 adds r3, #2 8000bba: 693a ldr r2, [r7, #16] 8000bbc: f841 2023 str.w r2, [r1, r3, lsl #2] /* Clear EXTI line configuration */ temp = EXTI->IMR; 8000bc0: 4b3a ldr r3, [pc, #232] ; (8000cac ) 8000bc2: 681b ldr r3, [r3, #0] 8000bc4: 613b str r3, [r7, #16] CLEAR_BIT(temp, (uint32_t)iocurrent); 8000bc6: 68fb ldr r3, [r7, #12] 8000bc8: 43db mvns r3, r3 8000bca: 693a ldr r2, [r7, #16] 8000bcc: 4013 ands r3, r2 8000bce: 613b str r3, [r7, #16] if ((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT) 8000bd0: 683b ldr r3, [r7, #0] 8000bd2: 685b ldr r3, [r3, #4] 8000bd4: f403 3380 and.w r3, r3, #65536 ; 0x10000 8000bd8: 2b00 cmp r3, #0 8000bda: d003 beq.n 8000be4 { SET_BIT(temp, iocurrent); 8000bdc: 693a ldr r2, [r7, #16] 8000bde: 68fb ldr r3, [r7, #12] 8000be0: 4313 orrs r3, r2 8000be2: 613b str r3, [r7, #16] } EXTI->IMR = temp; 8000be4: 4a31 ldr r2, [pc, #196] ; (8000cac ) 8000be6: 693b ldr r3, [r7, #16] 8000be8: 6013 str r3, [r2, #0] temp = EXTI->EMR; 8000bea: 4b30 ldr r3, [pc, #192] ; (8000cac ) 8000bec: 685b ldr r3, [r3, #4] 8000bee: 613b str r3, [r7, #16] CLEAR_BIT(temp, (uint32_t)iocurrent); 8000bf0: 68fb ldr r3, [r7, #12] 8000bf2: 43db mvns r3, r3 8000bf4: 693a ldr r2, [r7, #16] 8000bf6: 4013 ands r3, r2 8000bf8: 613b str r3, [r7, #16] if ((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT) 8000bfa: 683b ldr r3, [r7, #0] 8000bfc: 685b ldr r3, [r3, #4] 8000bfe: f403 3300 and.w r3, r3, #131072 ; 0x20000 8000c02: 2b00 cmp r3, #0 8000c04: d003 beq.n 8000c0e { SET_BIT(temp, iocurrent); 8000c06: 693a ldr r2, [r7, #16] 8000c08: 68fb ldr r3, [r7, #12] 8000c0a: 4313 orrs r3, r2 8000c0c: 613b str r3, [r7, #16] } EXTI->EMR = temp; 8000c0e: 4a27 ldr r2, [pc, #156] ; (8000cac ) 8000c10: 693b ldr r3, [r7, #16] 8000c12: 6053 str r3, [r2, #4] /* Clear Rising Falling edge configuration */ temp = EXTI->RTSR; 8000c14: 4b25 ldr r3, [pc, #148] ; (8000cac ) 8000c16: 689b ldr r3, [r3, #8] 8000c18: 613b str r3, [r7, #16] CLEAR_BIT(temp, (uint32_t)iocurrent); 8000c1a: 68fb ldr r3, [r7, #12] 8000c1c: 43db mvns r3, r3 8000c1e: 693a ldr r2, [r7, #16] 8000c20: 4013 ands r3, r2 8000c22: 613b str r3, [r7, #16] if ((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE) 8000c24: 683b ldr r3, [r7, #0] 8000c26: 685b ldr r3, [r3, #4] 8000c28: f403 1380 and.w r3, r3, #1048576 ; 0x100000 8000c2c: 2b00 cmp r3, #0 8000c2e: d003 beq.n 8000c38 { SET_BIT(temp, iocurrent); 8000c30: 693a ldr r2, [r7, #16] 8000c32: 68fb ldr r3, [r7, #12] 8000c34: 4313 orrs r3, r2 8000c36: 613b str r3, [r7, #16] } EXTI->RTSR = temp; 8000c38: 4a1c ldr r2, [pc, #112] ; (8000cac ) 8000c3a: 693b ldr r3, [r7, #16] 8000c3c: 6093 str r3, [r2, #8] temp = EXTI->FTSR; 8000c3e: 4b1b ldr r3, [pc, #108] ; (8000cac ) 8000c40: 68db ldr r3, [r3, #12] 8000c42: 613b str r3, [r7, #16] CLEAR_BIT(temp, (uint32_t)iocurrent); 8000c44: 68fb ldr r3, [r7, #12] 8000c46: 43db mvns r3, r3 8000c48: 693a ldr r2, [r7, #16] 8000c4a: 4013 ands r3, r2 8000c4c: 613b str r3, [r7, #16] if ((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE) 8000c4e: 683b ldr r3, [r7, #0] 8000c50: 685b ldr r3, [r3, #4] 8000c52: f403 1300 and.w r3, r3, #2097152 ; 0x200000 8000c56: 2b00 cmp r3, #0 8000c58: d003 beq.n 8000c62 { SET_BIT(temp, iocurrent); 8000c5a: 693a ldr r2, [r7, #16] 8000c5c: 68fb ldr r3, [r7, #12] 8000c5e: 4313 orrs r3, r2 8000c60: 613b str r3, [r7, #16] } EXTI->FTSR = temp; 8000c62: 4a12 ldr r2, [pc, #72] ; (8000cac ) 8000c64: 693b ldr r3, [r7, #16] 8000c66: 60d3 str r3, [r2, #12] } } position++; 8000c68: 697b ldr r3, [r7, #20] 8000c6a: 3301 adds r3, #1 8000c6c: 617b str r3, [r7, #20] while (((GPIO_Init->Pin) >> position) != 0) 8000c6e: 683b ldr r3, [r7, #0] 8000c70: 681a ldr r2, [r3, #0] 8000c72: 697b ldr r3, [r7, #20] 8000c74: fa22 f303 lsr.w r3, r2, r3 8000c78: 2b00 cmp r3, #0 8000c7a: f47f ae97 bne.w 80009ac } } 8000c7e: bf00 nop 8000c80: 371c adds r7, #28 8000c82: 46bd mov sp, r7 8000c84: bc80 pop {r7} 8000c86: 4770 bx lr 8000c88: 40023800 .word 0x40023800 8000c8c: 40010000 .word 0x40010000 8000c90: 40020000 .word 0x40020000 8000c94: 40020400 .word 0x40020400 8000c98: 40020800 .word 0x40020800 8000c9c: 40020c00 .word 0x40020c00 8000ca0: 40021000 .word 0x40021000 8000ca4: 40021400 .word 0x40021400 8000ca8: 40021800 .word 0x40021800 8000cac: 40010400 .word 0x40010400 08000cb0 : * @arg GPIO_PIN_RESET: to clear the port pin * @arg GPIO_PIN_SET: to set the port pin * @retval None */ void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) { 8000cb0: b480 push {r7} 8000cb2: b083 sub sp, #12 8000cb4: af00 add r7, sp, #0 8000cb6: 6078 str r0, [r7, #4] 8000cb8: 460b mov r3, r1 8000cba: 807b strh r3, [r7, #2] 8000cbc: 4613 mov r3, r2 8000cbe: 707b strb r3, [r7, #1] /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); assert_param(IS_GPIO_PIN_ACTION(PinState)); if (PinState != GPIO_PIN_RESET) 8000cc0: 787b ldrb r3, [r7, #1] 8000cc2: 2b00 cmp r3, #0 8000cc4: d003 beq.n 8000cce { GPIOx->BSRR = (uint32_t)GPIO_Pin; 8000cc6: 887a ldrh r2, [r7, #2] 8000cc8: 687b ldr r3, [r7, #4] 8000cca: 619a str r2, [r3, #24] } else { GPIOx->BSRR = (uint32_t)GPIO_Pin << 16 ; } } 8000ccc: e003 b.n 8000cd6 GPIOx->BSRR = (uint32_t)GPIO_Pin << 16 ; 8000cce: 887b ldrh r3, [r7, #2] 8000cd0: 041a lsls r2, r3, #16 8000cd2: 687b ldr r3, [r7, #4] 8000cd4: 619a str r2, [r3, #24] } 8000cd6: bf00 nop 8000cd8: 370c adds r7, #12 8000cda: 46bd mov sp, r7 8000cdc: bc80 pop {r7} 8000cde: 4770 bx lr 08000ce0 : * @param GPIOx where x can be (A..G depending on device used) to select the GPIO peripheral for STM32L1XX family devices * @param GPIO_Pin specifies the pins to be toggled. * @retval None */ void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) { 8000ce0: b480 push {r7} 8000ce2: b085 sub sp, #20 8000ce4: af00 add r7, sp, #0 8000ce6: 6078 str r0, [r7, #4] 8000ce8: 460b mov r3, r1 8000cea: 807b strh r3, [r7, #2] /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); /* get current Ouput Data Register value */ odr = GPIOx->ODR; 8000cec: 687b ldr r3, [r7, #4] 8000cee: 695b ldr r3, [r3, #20] 8000cf0: 60fb str r3, [r7, #12] /* Set selected pins that were at low level, and reset ones that were high */ GPIOx->BSRR = ((odr & GPIO_Pin) << GPIO_NUMBER) | (~odr & GPIO_Pin); 8000cf2: 887a ldrh r2, [r7, #2] 8000cf4: 68fb ldr r3, [r7, #12] 8000cf6: 4013 ands r3, r2 8000cf8: 041a lsls r2, r3, #16 8000cfa: 68fb ldr r3, [r7, #12] 8000cfc: 43d9 mvns r1, r3 8000cfe: 887b ldrh r3, [r7, #2] 8000d00: 400b ands r3, r1 8000d02: 431a orrs r2, r3 8000d04: 687b ldr r3, [r7, #4] 8000d06: 619a str r2, [r3, #24] } 8000d08: bf00 nop 8000d0a: 3714 adds r7, #20 8000d0c: 46bd mov sp, r7 8000d0e: bc80 pop {r7} 8000d10: 4770 bx lr ... 08000d14 : * supported by this macro. User should request a transition to HSE Off * first and then HSE On or HSE Bypass. * @retval HAL status */ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { 8000d14: b580 push {r7, lr} 8000d16: b088 sub sp, #32 8000d18: af00 add r7, sp, #0 8000d1a: 6078 str r0, [r7, #4] uint32_t tickstart; HAL_StatusTypeDef status; uint32_t sysclk_source, pll_config; /* Check the parameters */ if(RCC_OscInitStruct == NULL) 8000d1c: 687b ldr r3, [r7, #4] 8000d1e: 2b00 cmp r3, #0 8000d20: d101 bne.n 8000d26 { return HAL_ERROR; 8000d22: 2301 movs r3, #1 8000d24: e31d b.n 8001362 } assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); sysclk_source = __HAL_RCC_GET_SYSCLK_SOURCE(); 8000d26: 4b94 ldr r3, [pc, #592] ; (8000f78 ) 8000d28: 689b ldr r3, [r3, #8] 8000d2a: f003 030c and.w r3, r3, #12 8000d2e: 61bb str r3, [r7, #24] pll_config = __HAL_RCC_GET_PLL_OSCSOURCE(); 8000d30: 4b91 ldr r3, [pc, #580] ; (8000f78 ) 8000d32: 689b ldr r3, [r3, #8] 8000d34: f403 3380 and.w r3, r3, #65536 ; 0x10000 8000d38: 617b str r3, [r7, #20] /*------------------------------- HSE Configuration ------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) 8000d3a: 687b ldr r3, [r7, #4] 8000d3c: 681b ldr r3, [r3, #0] 8000d3e: f003 0301 and.w r3, r3, #1 8000d42: 2b00 cmp r3, #0 8000d44: d07b beq.n 8000e3e { /* Check the parameters */ assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */ if((sysclk_source == RCC_SYSCLKSOURCE_STATUS_HSE) 8000d46: 69bb ldr r3, [r7, #24] 8000d48: 2b08 cmp r3, #8 8000d4a: d006 beq.n 8000d5a || ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (pll_config == RCC_PLLSOURCE_HSE))) 8000d4c: 69bb ldr r3, [r7, #24] 8000d4e: 2b0c cmp r3, #12 8000d50: d10f bne.n 8000d72 8000d52: 697b ldr r3, [r7, #20] 8000d54: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 8000d58: d10b bne.n 8000d72 { if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 8000d5a: 4b87 ldr r3, [pc, #540] ; (8000f78 ) 8000d5c: 681b ldr r3, [r3, #0] 8000d5e: f403 3300 and.w r3, r3, #131072 ; 0x20000 8000d62: 2b00 cmp r3, #0 8000d64: d06a beq.n 8000e3c 8000d66: 687b ldr r3, [r7, #4] 8000d68: 685b ldr r3, [r3, #4] 8000d6a: 2b00 cmp r3, #0 8000d6c: d166 bne.n 8000e3c { return HAL_ERROR; 8000d6e: 2301 movs r3, #1 8000d70: e2f7 b.n 8001362 } } else { /* Set the new HSE configuration ---------------------------------------*/ __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); 8000d72: 687b ldr r3, [r7, #4] 8000d74: 685b ldr r3, [r3, #4] 8000d76: 2b01 cmp r3, #1 8000d78: d106 bne.n 8000d88 8000d7a: 4b7f ldr r3, [pc, #508] ; (8000f78 ) 8000d7c: 681b ldr r3, [r3, #0] 8000d7e: 4a7e ldr r2, [pc, #504] ; (8000f78 ) 8000d80: f443 3380 orr.w r3, r3, #65536 ; 0x10000 8000d84: 6013 str r3, [r2, #0] 8000d86: e02d b.n 8000de4 8000d88: 687b ldr r3, [r7, #4] 8000d8a: 685b ldr r3, [r3, #4] 8000d8c: 2b00 cmp r3, #0 8000d8e: d10c bne.n 8000daa 8000d90: 4b79 ldr r3, [pc, #484] ; (8000f78 ) 8000d92: 681b ldr r3, [r3, #0] 8000d94: 4a78 ldr r2, [pc, #480] ; (8000f78 ) 8000d96: f423 3380 bic.w r3, r3, #65536 ; 0x10000 8000d9a: 6013 str r3, [r2, #0] 8000d9c: 4b76 ldr r3, [pc, #472] ; (8000f78 ) 8000d9e: 681b ldr r3, [r3, #0] 8000da0: 4a75 ldr r2, [pc, #468] ; (8000f78 ) 8000da2: f423 2380 bic.w r3, r3, #262144 ; 0x40000 8000da6: 6013 str r3, [r2, #0] 8000da8: e01c b.n 8000de4 8000daa: 687b ldr r3, [r7, #4] 8000dac: 685b ldr r3, [r3, #4] 8000dae: 2b05 cmp r3, #5 8000db0: d10c bne.n 8000dcc 8000db2: 4b71 ldr r3, [pc, #452] ; (8000f78 ) 8000db4: 681b ldr r3, [r3, #0] 8000db6: 4a70 ldr r2, [pc, #448] ; (8000f78 ) 8000db8: f443 2380 orr.w r3, r3, #262144 ; 0x40000 8000dbc: 6013 str r3, [r2, #0] 8000dbe: 4b6e ldr r3, [pc, #440] ; (8000f78 ) 8000dc0: 681b ldr r3, [r3, #0] 8000dc2: 4a6d ldr r2, [pc, #436] ; (8000f78 ) 8000dc4: f443 3380 orr.w r3, r3, #65536 ; 0x10000 8000dc8: 6013 str r3, [r2, #0] 8000dca: e00b b.n 8000de4 8000dcc: 4b6a ldr r3, [pc, #424] ; (8000f78 ) 8000dce: 681b ldr r3, [r3, #0] 8000dd0: 4a69 ldr r2, [pc, #420] ; (8000f78 ) 8000dd2: f423 3380 bic.w r3, r3, #65536 ; 0x10000 8000dd6: 6013 str r3, [r2, #0] 8000dd8: 4b67 ldr r3, [pc, #412] ; (8000f78 ) 8000dda: 681b ldr r3, [r3, #0] 8000ddc: 4a66 ldr r2, [pc, #408] ; (8000f78 ) 8000dde: f423 2380 bic.w r3, r3, #262144 ; 0x40000 8000de2: 6013 str r3, [r2, #0] /* Check the HSE State */ if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF) 8000de4: 687b ldr r3, [r7, #4] 8000de6: 685b ldr r3, [r3, #4] 8000de8: 2b00 cmp r3, #0 8000dea: d013 beq.n 8000e14 { /* Get Start Tick */ tickstart = HAL_GetTick(); 8000dec: f7ff fcc2 bl 8000774 8000df0: 6138 str r0, [r7, #16] /* Wait till HSE is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U) 8000df2: e008 b.n 8000e06 { if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) 8000df4: f7ff fcbe bl 8000774 8000df8: 4602 mov r2, r0 8000dfa: 693b ldr r3, [r7, #16] 8000dfc: 1ad3 subs r3, r2, r3 8000dfe: 2b64 cmp r3, #100 ; 0x64 8000e00: d901 bls.n 8000e06 { return HAL_TIMEOUT; 8000e02: 2303 movs r3, #3 8000e04: e2ad b.n 8001362 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U) 8000e06: 4b5c ldr r3, [pc, #368] ; (8000f78 ) 8000e08: 681b ldr r3, [r3, #0] 8000e0a: f403 3300 and.w r3, r3, #131072 ; 0x20000 8000e0e: 2b00 cmp r3, #0 8000e10: d0f0 beq.n 8000df4 8000e12: e014 b.n 8000e3e } } else { /* Get Start Tick */ tickstart = HAL_GetTick(); 8000e14: f7ff fcae bl 8000774 8000e18: 6138 str r0, [r7, #16] /* Wait till HSE is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) 8000e1a: e008 b.n 8000e2e { if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) 8000e1c: f7ff fcaa bl 8000774 8000e20: 4602 mov r2, r0 8000e22: 693b ldr r3, [r7, #16] 8000e24: 1ad3 subs r3, r2, r3 8000e26: 2b64 cmp r3, #100 ; 0x64 8000e28: d901 bls.n 8000e2e { return HAL_TIMEOUT; 8000e2a: 2303 movs r3, #3 8000e2c: e299 b.n 8001362 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) 8000e2e: 4b52 ldr r3, [pc, #328] ; (8000f78 ) 8000e30: 681b ldr r3, [r3, #0] 8000e32: f403 3300 and.w r3, r3, #131072 ; 0x20000 8000e36: 2b00 cmp r3, #0 8000e38: d1f0 bne.n 8000e1c 8000e3a: e000 b.n 8000e3e if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 8000e3c: bf00 nop } } } } /*----------------------------- HSI Configuration --------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) 8000e3e: 687b ldr r3, [r7, #4] 8000e40: 681b ldr r3, [r3, #0] 8000e42: f003 0302 and.w r3, r3, #2 8000e46: 2b00 cmp r3, #0 8000e48: d05a beq.n 8000f00 /* Check the parameters */ assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ if((sysclk_source == RCC_SYSCLKSOURCE_STATUS_HSI) 8000e4a: 69bb ldr r3, [r7, #24] 8000e4c: 2b04 cmp r3, #4 8000e4e: d005 beq.n 8000e5c || ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (pll_config == RCC_PLLSOURCE_HSI))) 8000e50: 69bb ldr r3, [r7, #24] 8000e52: 2b0c cmp r3, #12 8000e54: d119 bne.n 8000e8a 8000e56: 697b ldr r3, [r7, #20] 8000e58: 2b00 cmp r3, #0 8000e5a: d116 bne.n 8000e8a { /* When HSI is used as system clock it will not disabled */ if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) 8000e5c: 4b46 ldr r3, [pc, #280] ; (8000f78 ) 8000e5e: 681b ldr r3, [r3, #0] 8000e60: f003 0302 and.w r3, r3, #2 8000e64: 2b00 cmp r3, #0 8000e66: d005 beq.n 8000e74 8000e68: 687b ldr r3, [r7, #4] 8000e6a: 68db ldr r3, [r3, #12] 8000e6c: 2b01 cmp r3, #1 8000e6e: d001 beq.n 8000e74 { return HAL_ERROR; 8000e70: 2301 movs r3, #1 8000e72: e276 b.n 8001362 } /* Otherwise, just the calibration is allowed */ else { /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 8000e74: 4b40 ldr r3, [pc, #256] ; (8000f78 ) 8000e76: 685b ldr r3, [r3, #4] 8000e78: f423 52f8 bic.w r2, r3, #7936 ; 0x1f00 8000e7c: 687b ldr r3, [r7, #4] 8000e7e: 691b ldr r3, [r3, #16] 8000e80: 021b lsls r3, r3, #8 8000e82: 493d ldr r1, [pc, #244] ; (8000f78 ) 8000e84: 4313 orrs r3, r2 8000e86: 604b str r3, [r1, #4] if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) 8000e88: e03a b.n 8000f00 } } else { /* Check the HSI State */ if(RCC_OscInitStruct->HSIState != RCC_HSI_OFF) 8000e8a: 687b ldr r3, [r7, #4] 8000e8c: 68db ldr r3, [r3, #12] 8000e8e: 2b00 cmp r3, #0 8000e90: d020 beq.n 8000ed4 { /* Enable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_ENABLE(); 8000e92: 4b3a ldr r3, [pc, #232] ; (8000f7c ) 8000e94: 2201 movs r2, #1 8000e96: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8000e98: f7ff fc6c bl 8000774 8000e9c: 6138 str r0, [r7, #16] /* Wait till HSI is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) 8000e9e: e008 b.n 8000eb2 { if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) 8000ea0: f7ff fc68 bl 8000774 8000ea4: 4602 mov r2, r0 8000ea6: 693b ldr r3, [r7, #16] 8000ea8: 1ad3 subs r3, r2, r3 8000eaa: 2b02 cmp r3, #2 8000eac: d901 bls.n 8000eb2 { return HAL_TIMEOUT; 8000eae: 2303 movs r3, #3 8000eb0: e257 b.n 8001362 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) 8000eb2: 4b31 ldr r3, [pc, #196] ; (8000f78 ) 8000eb4: 681b ldr r3, [r3, #0] 8000eb6: f003 0302 and.w r3, r3, #2 8000eba: 2b00 cmp r3, #0 8000ebc: d0f0 beq.n 8000ea0 } } /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 8000ebe: 4b2e ldr r3, [pc, #184] ; (8000f78 ) 8000ec0: 685b ldr r3, [r3, #4] 8000ec2: f423 52f8 bic.w r2, r3, #7936 ; 0x1f00 8000ec6: 687b ldr r3, [r7, #4] 8000ec8: 691b ldr r3, [r3, #16] 8000eca: 021b lsls r3, r3, #8 8000ecc: 492a ldr r1, [pc, #168] ; (8000f78 ) 8000ece: 4313 orrs r3, r2 8000ed0: 604b str r3, [r1, #4] 8000ed2: e015 b.n 8000f00 } else { /* Disable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_DISABLE(); 8000ed4: 4b29 ldr r3, [pc, #164] ; (8000f7c ) 8000ed6: 2200 movs r2, #0 8000ed8: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8000eda: f7ff fc4b bl 8000774 8000ede: 6138 str r0, [r7, #16] /* Wait till HSI is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) 8000ee0: e008 b.n 8000ef4 { if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) 8000ee2: f7ff fc47 bl 8000774 8000ee6: 4602 mov r2, r0 8000ee8: 693b ldr r3, [r7, #16] 8000eea: 1ad3 subs r3, r2, r3 8000eec: 2b02 cmp r3, #2 8000eee: d901 bls.n 8000ef4 { return HAL_TIMEOUT; 8000ef0: 2303 movs r3, #3 8000ef2: e236 b.n 8001362 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) 8000ef4: 4b20 ldr r3, [pc, #128] ; (8000f78 ) 8000ef6: 681b ldr r3, [r3, #0] 8000ef8: f003 0302 and.w r3, r3, #2 8000efc: 2b00 cmp r3, #0 8000efe: d1f0 bne.n 8000ee2 } } } } /*----------------------------- MSI Configuration --------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI) 8000f00: 687b ldr r3, [r7, #4] 8000f02: 681b ldr r3, [r3, #0] 8000f04: f003 0310 and.w r3, r3, #16 8000f08: 2b00 cmp r3, #0 8000f0a: f000 80b8 beq.w 800107e { /* When the MSI is used as system clock it will not be disabled */ if(sysclk_source == RCC_CFGR_SWS_MSI) 8000f0e: 69bb ldr r3, [r7, #24] 8000f10: 2b00 cmp r3, #0 8000f12: d170 bne.n 8000ff6 { if((__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) != 0U) && (RCC_OscInitStruct->MSIState == RCC_MSI_OFF)) 8000f14: 4b18 ldr r3, [pc, #96] ; (8000f78 ) 8000f16: 681b ldr r3, [r3, #0] 8000f18: f403 7300 and.w r3, r3, #512 ; 0x200 8000f1c: 2b00 cmp r3, #0 8000f1e: d005 beq.n 8000f2c 8000f20: 687b ldr r3, [r7, #4] 8000f22: 699b ldr r3, [r3, #24] 8000f24: 2b00 cmp r3, #0 8000f26: d101 bne.n 8000f2c { return HAL_ERROR; 8000f28: 2301 movs r3, #1 8000f2a: e21a b.n 8001362 assert_param(IS_RCC_MSI_CLOCK_RANGE(RCC_OscInitStruct->MSIClockRange)); /* To correctly read data from FLASH memory, the number of wait states (LATENCY) must be correctly programmed according to the frequency of the CPU clock (HCLK) and the supply voltage of the device. */ if(RCC_OscInitStruct->MSIClockRange > __HAL_RCC_GET_MSI_RANGE()) 8000f2c: 687b ldr r3, [r7, #4] 8000f2e: 6a1a ldr r2, [r3, #32] 8000f30: 4b11 ldr r3, [pc, #68] ; (8000f78 ) 8000f32: 685b ldr r3, [r3, #4] 8000f34: f403 4360 and.w r3, r3, #57344 ; 0xe000 8000f38: 429a cmp r2, r3 8000f3a: d921 bls.n 8000f80 { /* First increase number of wait states update if necessary */ if(RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK) 8000f3c: 687b ldr r3, [r7, #4] 8000f3e: 6a1b ldr r3, [r3, #32] 8000f40: 4618 mov r0, r3 8000f42: f000 fbed bl 8001720 8000f46: 4603 mov r3, r0 8000f48: 2b00 cmp r3, #0 8000f4a: d001 beq.n 8000f50 { return HAL_ERROR; 8000f4c: 2301 movs r3, #1 8000f4e: e208 b.n 8001362 } /* Selects the Multiple Speed oscillator (MSI) clock range .*/ __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange); 8000f50: 4b09 ldr r3, [pc, #36] ; (8000f78 ) 8000f52: 685b ldr r3, [r3, #4] 8000f54: f423 4260 bic.w r2, r3, #57344 ; 0xe000 8000f58: 687b ldr r3, [r7, #4] 8000f5a: 6a1b ldr r3, [r3, #32] 8000f5c: 4906 ldr r1, [pc, #24] ; (8000f78 ) 8000f5e: 4313 orrs r3, r2 8000f60: 604b str r3, [r1, #4] /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/ __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue); 8000f62: 4b05 ldr r3, [pc, #20] ; (8000f78 ) 8000f64: 685b ldr r3, [r3, #4] 8000f66: f023 427f bic.w r2, r3, #4278190080 ; 0xff000000 8000f6a: 687b ldr r3, [r7, #4] 8000f6c: 69db ldr r3, [r3, #28] 8000f6e: 061b lsls r3, r3, #24 8000f70: 4901 ldr r1, [pc, #4] ; (8000f78 ) 8000f72: 4313 orrs r3, r2 8000f74: 604b str r3, [r1, #4] 8000f76: e020 b.n 8000fba 8000f78: 40023800 .word 0x40023800 8000f7c: 42470000 .word 0x42470000 } else { /* Else, keep current flash latency while decreasing applies */ /* Selects the Multiple Speed oscillator (MSI) clock range .*/ __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange); 8000f80: 4ba4 ldr r3, [pc, #656] ; (8001214 ) 8000f82: 685b ldr r3, [r3, #4] 8000f84: f423 4260 bic.w r2, r3, #57344 ; 0xe000 8000f88: 687b ldr r3, [r7, #4] 8000f8a: 6a1b ldr r3, [r3, #32] 8000f8c: 49a1 ldr r1, [pc, #644] ; (8001214 ) 8000f8e: 4313 orrs r3, r2 8000f90: 604b str r3, [r1, #4] /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/ __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue); 8000f92: 4ba0 ldr r3, [pc, #640] ; (8001214 ) 8000f94: 685b ldr r3, [r3, #4] 8000f96: f023 427f bic.w r2, r3, #4278190080 ; 0xff000000 8000f9a: 687b ldr r3, [r7, #4] 8000f9c: 69db ldr r3, [r3, #28] 8000f9e: 061b lsls r3, r3, #24 8000fa0: 499c ldr r1, [pc, #624] ; (8001214 ) 8000fa2: 4313 orrs r3, r2 8000fa4: 604b str r3, [r1, #4] /* Decrease number of wait states update if necessary */ if(RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK) 8000fa6: 687b ldr r3, [r7, #4] 8000fa8: 6a1b ldr r3, [r3, #32] 8000faa: 4618 mov r0, r3 8000fac: f000 fbb8 bl 8001720 8000fb0: 4603 mov r3, r0 8000fb2: 2b00 cmp r3, #0 8000fb4: d001 beq.n 8000fba { return HAL_ERROR; 8000fb6: 2301 movs r3, #1 8000fb8: e1d3 b.n 8001362 } } /* Update the SystemCoreClock global variable */ SystemCoreClock = (32768U * (1UL << ((RCC_OscInitStruct->MSIClockRange >> RCC_ICSCR_MSIRANGE_Pos) + 1U))) 8000fba: 687b ldr r3, [r7, #4] 8000fbc: 6a1b ldr r3, [r3, #32] 8000fbe: 0b5b lsrs r3, r3, #13 8000fc0: 3301 adds r3, #1 8000fc2: f44f 4200 mov.w r2, #32768 ; 0x8000 8000fc6: fa02 f303 lsl.w r3, r2, r3 >> AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)]; 8000fca: 4a92 ldr r2, [pc, #584] ; (8001214 ) 8000fcc: 6892 ldr r2, [r2, #8] 8000fce: 0912 lsrs r2, r2, #4 8000fd0: f002 020f and.w r2, r2, #15 8000fd4: 4990 ldr r1, [pc, #576] ; (8001218 ) 8000fd6: 5c8a ldrb r2, [r1, r2] 8000fd8: 40d3 lsrs r3, r2 SystemCoreClock = (32768U * (1UL << ((RCC_OscInitStruct->MSIClockRange >> RCC_ICSCR_MSIRANGE_Pos) + 1U))) 8000fda: 4a90 ldr r2, [pc, #576] ; (800121c ) 8000fdc: 6013 str r3, [r2, #0] /* Configure the source of time base considering new system clocks settings*/ status = HAL_InitTick(uwTickPrio); 8000fde: 4b90 ldr r3, [pc, #576] ; (8001220 ) 8000fe0: 681b ldr r3, [r3, #0] 8000fe2: 4618 mov r0, r3 8000fe4: f7ff fb7a bl 80006dc 8000fe8: 4603 mov r3, r0 8000fea: 73fb strb r3, [r7, #15] if(status != HAL_OK) 8000fec: 7bfb ldrb r3, [r7, #15] 8000fee: 2b00 cmp r3, #0 8000ff0: d045 beq.n 800107e { return status; 8000ff2: 7bfb ldrb r3, [r7, #15] 8000ff4: e1b5 b.n 8001362 { /* Check MSI State */ assert_param(IS_RCC_MSI(RCC_OscInitStruct->MSIState)); /* Check the MSI State */ if(RCC_OscInitStruct->MSIState != RCC_MSI_OFF) 8000ff6: 687b ldr r3, [r7, #4] 8000ff8: 699b ldr r3, [r3, #24] 8000ffa: 2b00 cmp r3, #0 8000ffc: d029 beq.n 8001052 { /* Enable the Multi Speed oscillator (MSI). */ __HAL_RCC_MSI_ENABLE(); 8000ffe: 4b89 ldr r3, [pc, #548] ; (8001224 ) 8001000: 2201 movs r2, #1 8001002: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8001004: f7ff fbb6 bl 8000774 8001008: 6138 str r0, [r7, #16] /* Wait till MSI is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) == 0U) 800100a: e008 b.n 800101e { if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE) 800100c: f7ff fbb2 bl 8000774 8001010: 4602 mov r2, r0 8001012: 693b ldr r3, [r7, #16] 8001014: 1ad3 subs r3, r2, r3 8001016: 2b02 cmp r3, #2 8001018: d901 bls.n 800101e { return HAL_TIMEOUT; 800101a: 2303 movs r3, #3 800101c: e1a1 b.n 8001362 while(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) == 0U) 800101e: 4b7d ldr r3, [pc, #500] ; (8001214 ) 8001020: 681b ldr r3, [r3, #0] 8001022: f403 7300 and.w r3, r3, #512 ; 0x200 8001026: 2b00 cmp r3, #0 8001028: d0f0 beq.n 800100c /* Check MSICalibrationValue and MSIClockRange input parameters */ assert_param(IS_RCC_MSICALIBRATION_VALUE(RCC_OscInitStruct->MSICalibrationValue)); assert_param(IS_RCC_MSI_CLOCK_RANGE(RCC_OscInitStruct->MSIClockRange)); /* Selects the Multiple Speed oscillator (MSI) clock range .*/ __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange); 800102a: 4b7a ldr r3, [pc, #488] ; (8001214 ) 800102c: 685b ldr r3, [r3, #4] 800102e: f423 4260 bic.w r2, r3, #57344 ; 0xe000 8001032: 687b ldr r3, [r7, #4] 8001034: 6a1b ldr r3, [r3, #32] 8001036: 4977 ldr r1, [pc, #476] ; (8001214 ) 8001038: 4313 orrs r3, r2 800103a: 604b str r3, [r1, #4] /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/ __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue); 800103c: 4b75 ldr r3, [pc, #468] ; (8001214 ) 800103e: 685b ldr r3, [r3, #4] 8001040: f023 427f bic.w r2, r3, #4278190080 ; 0xff000000 8001044: 687b ldr r3, [r7, #4] 8001046: 69db ldr r3, [r3, #28] 8001048: 061b lsls r3, r3, #24 800104a: 4972 ldr r1, [pc, #456] ; (8001214 ) 800104c: 4313 orrs r3, r2 800104e: 604b str r3, [r1, #4] 8001050: e015 b.n 800107e } else { /* Disable the Multi Speed oscillator (MSI). */ __HAL_RCC_MSI_DISABLE(); 8001052: 4b74 ldr r3, [pc, #464] ; (8001224 ) 8001054: 2200 movs r2, #0 8001056: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8001058: f7ff fb8c bl 8000774 800105c: 6138 str r0, [r7, #16] /* Wait till MSI is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) != 0U) 800105e: e008 b.n 8001072 { if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE) 8001060: f7ff fb88 bl 8000774 8001064: 4602 mov r2, r0 8001066: 693b ldr r3, [r7, #16] 8001068: 1ad3 subs r3, r2, r3 800106a: 2b02 cmp r3, #2 800106c: d901 bls.n 8001072 { return HAL_TIMEOUT; 800106e: 2303 movs r3, #3 8001070: e177 b.n 8001362 while(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) != 0U) 8001072: 4b68 ldr r3, [pc, #416] ; (8001214 ) 8001074: 681b ldr r3, [r3, #0] 8001076: f403 7300 and.w r3, r3, #512 ; 0x200 800107a: 2b00 cmp r3, #0 800107c: d1f0 bne.n 8001060 } } } } /*------------------------------ LSI Configuration -------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) 800107e: 687b ldr r3, [r7, #4] 8001080: 681b ldr r3, [r3, #0] 8001082: f003 0308 and.w r3, r3, #8 8001086: 2b00 cmp r3, #0 8001088: d030 beq.n 80010ec { /* Check the parameters */ assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); /* Check the LSI State */ if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF) 800108a: 687b ldr r3, [r7, #4] 800108c: 695b ldr r3, [r3, #20] 800108e: 2b00 cmp r3, #0 8001090: d016 beq.n 80010c0 { /* Enable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_ENABLE(); 8001092: 4b65 ldr r3, [pc, #404] ; (8001228 ) 8001094: 2201 movs r2, #1 8001096: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8001098: f7ff fb6c bl 8000774 800109c: 6138 str r0, [r7, #16] /* Wait till LSI is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == 0U) 800109e: e008 b.n 80010b2 { if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) 80010a0: f7ff fb68 bl 8000774 80010a4: 4602 mov r2, r0 80010a6: 693b ldr r3, [r7, #16] 80010a8: 1ad3 subs r3, r2, r3 80010aa: 2b02 cmp r3, #2 80010ac: d901 bls.n 80010b2 { return HAL_TIMEOUT; 80010ae: 2303 movs r3, #3 80010b0: e157 b.n 8001362 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == 0U) 80010b2: 4b58 ldr r3, [pc, #352] ; (8001214 ) 80010b4: 6b5b ldr r3, [r3, #52] ; 0x34 80010b6: f003 0302 and.w r3, r3, #2 80010ba: 2b00 cmp r3, #0 80010bc: d0f0 beq.n 80010a0 80010be: e015 b.n 80010ec } } else { /* Disable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_DISABLE(); 80010c0: 4b59 ldr r3, [pc, #356] ; (8001228 ) 80010c2: 2200 movs r2, #0 80010c4: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 80010c6: f7ff fb55 bl 8000774 80010ca: 6138 str r0, [r7, #16] /* Wait till LSI is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != 0U) 80010cc: e008 b.n 80010e0 { if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) 80010ce: f7ff fb51 bl 8000774 80010d2: 4602 mov r2, r0 80010d4: 693b ldr r3, [r7, #16] 80010d6: 1ad3 subs r3, r2, r3 80010d8: 2b02 cmp r3, #2 80010da: d901 bls.n 80010e0 { return HAL_TIMEOUT; 80010dc: 2303 movs r3, #3 80010de: e140 b.n 8001362 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != 0U) 80010e0: 4b4c ldr r3, [pc, #304] ; (8001214 ) 80010e2: 6b5b ldr r3, [r3, #52] ; 0x34 80010e4: f003 0302 and.w r3, r3, #2 80010e8: 2b00 cmp r3, #0 80010ea: d1f0 bne.n 80010ce } } } } /*------------------------------ LSE Configuration -------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) 80010ec: 687b ldr r3, [r7, #4] 80010ee: 681b ldr r3, [r3, #0] 80010f0: f003 0304 and.w r3, r3, #4 80010f4: 2b00 cmp r3, #0 80010f6: f000 80b5 beq.w 8001264 { FlagStatus pwrclkchanged = RESET; 80010fa: 2300 movs r3, #0 80010fc: 77fb strb r3, [r7, #31] /* Check the parameters */ assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); /* Update LSE configuration in Backup Domain control register */ /* Requires to enable write access to Backup Domain of necessary */ if(__HAL_RCC_PWR_IS_CLK_DISABLED()) 80010fe: 4b45 ldr r3, [pc, #276] ; (8001214 ) 8001100: 6a5b ldr r3, [r3, #36] ; 0x24 8001102: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 8001106: 2b00 cmp r3, #0 8001108: d10d bne.n 8001126 { __HAL_RCC_PWR_CLK_ENABLE(); 800110a: 4b42 ldr r3, [pc, #264] ; (8001214 ) 800110c: 6a5b ldr r3, [r3, #36] ; 0x24 800110e: 4a41 ldr r2, [pc, #260] ; (8001214 ) 8001110: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 8001114: 6253 str r3, [r2, #36] ; 0x24 8001116: 4b3f ldr r3, [pc, #252] ; (8001214 ) 8001118: 6a5b ldr r3, [r3, #36] ; 0x24 800111a: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 800111e: 60bb str r3, [r7, #8] 8001120: 68bb ldr r3, [r7, #8] pwrclkchanged = SET; 8001122: 2301 movs r3, #1 8001124: 77fb strb r3, [r7, #31] } if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8001126: 4b41 ldr r3, [pc, #260] ; (800122c ) 8001128: 681b ldr r3, [r3, #0] 800112a: f403 7380 and.w r3, r3, #256 ; 0x100 800112e: 2b00 cmp r3, #0 8001130: d118 bne.n 8001164 { /* Enable write access to Backup domain */ SET_BIT(PWR->CR, PWR_CR_DBP); 8001132: 4b3e ldr r3, [pc, #248] ; (800122c ) 8001134: 681b ldr r3, [r3, #0] 8001136: 4a3d ldr r2, [pc, #244] ; (800122c ) 8001138: f443 7380 orr.w r3, r3, #256 ; 0x100 800113c: 6013 str r3, [r2, #0] /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); 800113e: f7ff fb19 bl 8000774 8001142: 6138 str r0, [r7, #16] while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8001144: e008 b.n 8001158 { if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 8001146: f7ff fb15 bl 8000774 800114a: 4602 mov r2, r0 800114c: 693b ldr r3, [r7, #16] 800114e: 1ad3 subs r3, r2, r3 8001150: 2b64 cmp r3, #100 ; 0x64 8001152: d901 bls.n 8001158 { return HAL_TIMEOUT; 8001154: 2303 movs r3, #3 8001156: e104 b.n 8001362 while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8001158: 4b34 ldr r3, [pc, #208] ; (800122c ) 800115a: 681b ldr r3, [r3, #0] 800115c: f403 7380 and.w r3, r3, #256 ; 0x100 8001160: 2b00 cmp r3, #0 8001162: d0f0 beq.n 8001146 } } } /* Set the new LSE configuration -----------------------------------------*/ __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); 8001164: 687b ldr r3, [r7, #4] 8001166: 689b ldr r3, [r3, #8] 8001168: 2b01 cmp r3, #1 800116a: d106 bne.n 800117a 800116c: 4b29 ldr r3, [pc, #164] ; (8001214 ) 800116e: 6b5b ldr r3, [r3, #52] ; 0x34 8001170: 4a28 ldr r2, [pc, #160] ; (8001214 ) 8001172: f443 7380 orr.w r3, r3, #256 ; 0x100 8001176: 6353 str r3, [r2, #52] ; 0x34 8001178: e02d b.n 80011d6 800117a: 687b ldr r3, [r7, #4] 800117c: 689b ldr r3, [r3, #8] 800117e: 2b00 cmp r3, #0 8001180: d10c bne.n 800119c 8001182: 4b24 ldr r3, [pc, #144] ; (8001214 ) 8001184: 6b5b ldr r3, [r3, #52] ; 0x34 8001186: 4a23 ldr r2, [pc, #140] ; (8001214 ) 8001188: f423 7380 bic.w r3, r3, #256 ; 0x100 800118c: 6353 str r3, [r2, #52] ; 0x34 800118e: 4b21 ldr r3, [pc, #132] ; (8001214 ) 8001190: 6b5b ldr r3, [r3, #52] ; 0x34 8001192: 4a20 ldr r2, [pc, #128] ; (8001214 ) 8001194: f423 6380 bic.w r3, r3, #1024 ; 0x400 8001198: 6353 str r3, [r2, #52] ; 0x34 800119a: e01c b.n 80011d6 800119c: 687b ldr r3, [r7, #4] 800119e: 689b ldr r3, [r3, #8] 80011a0: 2b05 cmp r3, #5 80011a2: d10c bne.n 80011be 80011a4: 4b1b ldr r3, [pc, #108] ; (8001214 ) 80011a6: 6b5b ldr r3, [r3, #52] ; 0x34 80011a8: 4a1a ldr r2, [pc, #104] ; (8001214 ) 80011aa: f443 6380 orr.w r3, r3, #1024 ; 0x400 80011ae: 6353 str r3, [r2, #52] ; 0x34 80011b0: 4b18 ldr r3, [pc, #96] ; (8001214 ) 80011b2: 6b5b ldr r3, [r3, #52] ; 0x34 80011b4: 4a17 ldr r2, [pc, #92] ; (8001214 ) 80011b6: f443 7380 orr.w r3, r3, #256 ; 0x100 80011ba: 6353 str r3, [r2, #52] ; 0x34 80011bc: e00b b.n 80011d6 80011be: 4b15 ldr r3, [pc, #84] ; (8001214 ) 80011c0: 6b5b ldr r3, [r3, #52] ; 0x34 80011c2: 4a14 ldr r2, [pc, #80] ; (8001214 ) 80011c4: f423 7380 bic.w r3, r3, #256 ; 0x100 80011c8: 6353 str r3, [r2, #52] ; 0x34 80011ca: 4b12 ldr r3, [pc, #72] ; (8001214 ) 80011cc: 6b5b ldr r3, [r3, #52] ; 0x34 80011ce: 4a11 ldr r2, [pc, #68] ; (8001214 ) 80011d0: f423 6380 bic.w r3, r3, #1024 ; 0x400 80011d4: 6353 str r3, [r2, #52] ; 0x34 /* Check the LSE State */ if(RCC_OscInitStruct->LSEState != RCC_LSE_OFF) 80011d6: 687b ldr r3, [r7, #4] 80011d8: 689b ldr r3, [r3, #8] 80011da: 2b00 cmp r3, #0 80011dc: d015 beq.n 800120a { /* Get Start Tick */ tickstart = HAL_GetTick(); 80011de: f7ff fac9 bl 8000774 80011e2: 6138 str r0, [r7, #16] /* Wait till LSE is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U) 80011e4: e00a b.n 80011fc { if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) 80011e6: f7ff fac5 bl 8000774 80011ea: 4602 mov r2, r0 80011ec: 693b ldr r3, [r7, #16] 80011ee: 1ad3 subs r3, r2, r3 80011f0: f241 3288 movw r2, #5000 ; 0x1388 80011f4: 4293 cmp r3, r2 80011f6: d901 bls.n 80011fc { return HAL_TIMEOUT; 80011f8: 2303 movs r3, #3 80011fa: e0b2 b.n 8001362 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U) 80011fc: 4b05 ldr r3, [pc, #20] ; (8001214 ) 80011fe: 6b5b ldr r3, [r3, #52] ; 0x34 8001200: f403 7300 and.w r3, r3, #512 ; 0x200 8001204: 2b00 cmp r3, #0 8001206: d0ee beq.n 80011e6 8001208: e023 b.n 8001252 } } else { /* Get Start Tick */ tickstart = HAL_GetTick(); 800120a: f7ff fab3 bl 8000774 800120e: 6138 str r0, [r7, #16] /* Wait till LSE is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != 0U) 8001210: e019 b.n 8001246 8001212: bf00 nop 8001214: 40023800 .word 0x40023800 8001218: 0800185c .word 0x0800185c 800121c: 20000000 .word 0x20000000 8001220: 20000004 .word 0x20000004 8001224: 42470020 .word 0x42470020 8001228: 42470680 .word 0x42470680 800122c: 40007000 .word 0x40007000 { if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) 8001230: f7ff faa0 bl 8000774 8001234: 4602 mov r2, r0 8001236: 693b ldr r3, [r7, #16] 8001238: 1ad3 subs r3, r2, r3 800123a: f241 3288 movw r2, #5000 ; 0x1388 800123e: 4293 cmp r3, r2 8001240: d901 bls.n 8001246 { return HAL_TIMEOUT; 8001242: 2303 movs r3, #3 8001244: e08d b.n 8001362 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != 0U) 8001246: 4b49 ldr r3, [pc, #292] ; (800136c ) 8001248: 6b5b ldr r3, [r3, #52] ; 0x34 800124a: f403 7300 and.w r3, r3, #512 ; 0x200 800124e: 2b00 cmp r3, #0 8001250: d1ee bne.n 8001230 } } } /* Require to disable power clock if necessary */ if(pwrclkchanged == SET) 8001252: 7ffb ldrb r3, [r7, #31] 8001254: 2b01 cmp r3, #1 8001256: d105 bne.n 8001264 { __HAL_RCC_PWR_CLK_DISABLE(); 8001258: 4b44 ldr r3, [pc, #272] ; (800136c ) 800125a: 6a5b ldr r3, [r3, #36] ; 0x24 800125c: 4a43 ldr r2, [pc, #268] ; (800136c ) 800125e: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000 8001262: 6253 str r3, [r2, #36] ; 0x24 } /*-------------------------------- PLL Configuration -----------------------*/ /* Check the parameters */ assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) 8001264: 687b ldr r3, [r7, #4] 8001266: 6a5b ldr r3, [r3, #36] ; 0x24 8001268: 2b00 cmp r3, #0 800126a: d079 beq.n 8001360 { /* Check if the PLL is used as system clock or not */ if(sysclk_source != RCC_SYSCLKSOURCE_STATUS_PLLCLK) 800126c: 69bb ldr r3, [r7, #24] 800126e: 2b0c cmp r3, #12 8001270: d056 beq.n 8001320 { if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) 8001272: 687b ldr r3, [r7, #4] 8001274: 6a5b ldr r3, [r3, #36] ; 0x24 8001276: 2b02 cmp r3, #2 8001278: d13b bne.n 80012f2 assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource)); assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL)); assert_param(IS_RCC_PLL_DIV(RCC_OscInitStruct->PLL.PLLDIV)); /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 800127a: 4b3d ldr r3, [pc, #244] ; (8001370 ) 800127c: 2200 movs r2, #0 800127e: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8001280: f7ff fa78 bl 8000774 8001284: 6138 str r0, [r7, #16] /* Wait till PLL is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U) 8001286: e008 b.n 800129a { if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) 8001288: f7ff fa74 bl 8000774 800128c: 4602 mov r2, r0 800128e: 693b ldr r3, [r7, #16] 8001290: 1ad3 subs r3, r2, r3 8001292: 2b02 cmp r3, #2 8001294: d901 bls.n 800129a { return HAL_TIMEOUT; 8001296: 2303 movs r3, #3 8001298: e063 b.n 8001362 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U) 800129a: 4b34 ldr r3, [pc, #208] ; (800136c ) 800129c: 681b ldr r3, [r3, #0] 800129e: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 80012a2: 2b00 cmp r3, #0 80012a4: d1f0 bne.n 8001288 } } /* Configure the main PLL clock source, multiplication and division factors. */ __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, 80012a6: 4b31 ldr r3, [pc, #196] ; (800136c ) 80012a8: 689b ldr r3, [r3, #8] 80012aa: f423 027d bic.w r2, r3, #16580608 ; 0xfd0000 80012ae: 687b ldr r3, [r7, #4] 80012b0: 6a99 ldr r1, [r3, #40] ; 0x28 80012b2: 687b ldr r3, [r7, #4] 80012b4: 6adb ldr r3, [r3, #44] ; 0x2c 80012b6: 4319 orrs r1, r3 80012b8: 687b ldr r3, [r7, #4] 80012ba: 6b1b ldr r3, [r3, #48] ; 0x30 80012bc: 430b orrs r3, r1 80012be: 492b ldr r1, [pc, #172] ; (800136c ) 80012c0: 4313 orrs r3, r2 80012c2: 608b str r3, [r1, #8] RCC_OscInitStruct->PLL.PLLMUL, RCC_OscInitStruct->PLL.PLLDIV); /* Enable the main PLL. */ __HAL_RCC_PLL_ENABLE(); 80012c4: 4b2a ldr r3, [pc, #168] ; (8001370 ) 80012c6: 2201 movs r2, #1 80012c8: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 80012ca: f7ff fa53 bl 8000774 80012ce: 6138 str r0, [r7, #16] /* Wait till PLL is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U) 80012d0: e008 b.n 80012e4 { if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) 80012d2: f7ff fa4f bl 8000774 80012d6: 4602 mov r2, r0 80012d8: 693b ldr r3, [r7, #16] 80012da: 1ad3 subs r3, r2, r3 80012dc: 2b02 cmp r3, #2 80012de: d901 bls.n 80012e4 { return HAL_TIMEOUT; 80012e0: 2303 movs r3, #3 80012e2: e03e b.n 8001362 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U) 80012e4: 4b21 ldr r3, [pc, #132] ; (800136c ) 80012e6: 681b ldr r3, [r3, #0] 80012e8: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 80012ec: 2b00 cmp r3, #0 80012ee: d0f0 beq.n 80012d2 80012f0: e036 b.n 8001360 } } else { /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 80012f2: 4b1f ldr r3, [pc, #124] ; (8001370 ) 80012f4: 2200 movs r2, #0 80012f6: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 80012f8: f7ff fa3c bl 8000774 80012fc: 6138 str r0, [r7, #16] /* Wait till PLL is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U) 80012fe: e008 b.n 8001312 { if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) 8001300: f7ff fa38 bl 8000774 8001304: 4602 mov r2, r0 8001306: 693b ldr r3, [r7, #16] 8001308: 1ad3 subs r3, r2, r3 800130a: 2b02 cmp r3, #2 800130c: d901 bls.n 8001312 { return HAL_TIMEOUT; 800130e: 2303 movs r3, #3 8001310: e027 b.n 8001362 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U) 8001312: 4b16 ldr r3, [pc, #88] ; (800136c ) 8001314: 681b ldr r3, [r3, #0] 8001316: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 800131a: 2b00 cmp r3, #0 800131c: d1f0 bne.n 8001300 800131e: e01f b.n 8001360 } } else { /* Check if there is a request to disable the PLL used as System clock source */ if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) 8001320: 687b ldr r3, [r7, #4] 8001322: 6a5b ldr r3, [r3, #36] ; 0x24 8001324: 2b01 cmp r3, #1 8001326: d101 bne.n 800132c { return HAL_ERROR; 8001328: 2301 movs r3, #1 800132a: e01a b.n 8001362 } else { /* Do not return HAL_ERROR if request repeats the current configuration */ pll_config = RCC->CFGR; 800132c: 4b0f ldr r3, [pc, #60] ; (800136c ) 800132e: 689b ldr r3, [r3, #8] 8001330: 617b str r3, [r7, #20] if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 8001332: 697b ldr r3, [r7, #20] 8001334: f403 3280 and.w r2, r3, #65536 ; 0x10000 8001338: 687b ldr r3, [r7, #4] 800133a: 6a9b ldr r3, [r3, #40] ; 0x28 800133c: 429a cmp r2, r3 800133e: d10d bne.n 800135c (READ_BIT(pll_config, RCC_CFGR_PLLMUL) != RCC_OscInitStruct->PLL.PLLMUL) || 8001340: 697b ldr r3, [r7, #20] 8001342: f403 1270 and.w r2, r3, #3932160 ; 0x3c0000 8001346: 687b ldr r3, [r7, #4] 8001348: 6adb ldr r3, [r3, #44] ; 0x2c if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 800134a: 429a cmp r2, r3 800134c: d106 bne.n 800135c (READ_BIT(pll_config, RCC_CFGR_PLLDIV) != RCC_OscInitStruct->PLL.PLLDIV)) 800134e: 697b ldr r3, [r7, #20] 8001350: f403 0240 and.w r2, r3, #12582912 ; 0xc00000 8001354: 687b ldr r3, [r7, #4] 8001356: 6b1b ldr r3, [r3, #48] ; 0x30 (READ_BIT(pll_config, RCC_CFGR_PLLMUL) != RCC_OscInitStruct->PLL.PLLMUL) || 8001358: 429a cmp r2, r3 800135a: d001 beq.n 8001360 { return HAL_ERROR; 800135c: 2301 movs r3, #1 800135e: e000 b.n 8001362 } } } } return HAL_OK; 8001360: 2300 movs r3, #0 } 8001362: 4618 mov r0, r3 8001364: 3720 adds r7, #32 8001366: 46bd mov sp, r7 8001368: bd80 pop {r7, pc} 800136a: bf00 nop 800136c: 40023800 .word 0x40023800 8001370: 42470060 .word 0x42470060 08001374 : * HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency * (for more details refer to section above "Initialization/de-initialization functions") * @retval HAL status */ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) { 8001374: b580 push {r7, lr} 8001376: b084 sub sp, #16 8001378: af00 add r7, sp, #0 800137a: 6078 str r0, [r7, #4] 800137c: 6039 str r1, [r7, #0] uint32_t tickstart; HAL_StatusTypeDef status; /* Check the parameters */ if(RCC_ClkInitStruct == NULL) 800137e: 687b ldr r3, [r7, #4] 8001380: 2b00 cmp r3, #0 8001382: d101 bne.n 8001388 { return HAL_ERROR; 8001384: 2301 movs r3, #1 8001386: e11a b.n 80015be /* To correctly read data from FLASH memory, the number of wait states (LATENCY) must be correctly programmed according to the frequency of the CPU clock (HCLK) and the supply voltage of the device. */ /* Increasing the number of wait states because of higher CPU frequency */ if(FLatency > __HAL_FLASH_GET_LATENCY()) 8001388: 4b8f ldr r3, [pc, #572] ; (80015c8 ) 800138a: 681b ldr r3, [r3, #0] 800138c: f003 0301 and.w r3, r3, #1 8001390: 683a ldr r2, [r7, #0] 8001392: 429a cmp r2, r3 8001394: d919 bls.n 80013ca { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 8001396: 683b ldr r3, [r7, #0] 8001398: 2b01 cmp r3, #1 800139a: d105 bne.n 80013a8 800139c: 4b8a ldr r3, [pc, #552] ; (80015c8 ) 800139e: 681b ldr r3, [r3, #0] 80013a0: 4a89 ldr r2, [pc, #548] ; (80015c8 ) 80013a2: f043 0304 orr.w r3, r3, #4 80013a6: 6013 str r3, [r2, #0] 80013a8: 4b87 ldr r3, [pc, #540] ; (80015c8 ) 80013aa: 681b ldr r3, [r3, #0] 80013ac: f023 0201 bic.w r2, r3, #1 80013b0: 4985 ldr r1, [pc, #532] ; (80015c8 ) 80013b2: 683b ldr r3, [r7, #0] 80013b4: 4313 orrs r3, r2 80013b6: 600b str r3, [r1, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if(__HAL_FLASH_GET_LATENCY() != FLatency) 80013b8: 4b83 ldr r3, [pc, #524] ; (80015c8 ) 80013ba: 681b ldr r3, [r3, #0] 80013bc: f003 0301 and.w r3, r3, #1 80013c0: 683a ldr r2, [r7, #0] 80013c2: 429a cmp r2, r3 80013c4: d001 beq.n 80013ca { return HAL_ERROR; 80013c6: 2301 movs r3, #1 80013c8: e0f9 b.n 80015be } } /*-------------------------- HCLK Configuration --------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) 80013ca: 687b ldr r3, [r7, #4] 80013cc: 681b ldr r3, [r3, #0] 80013ce: f003 0302 and.w r3, r3, #2 80013d2: 2b00 cmp r3, #0 80013d4: d008 beq.n 80013e8 { assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); 80013d6: 4b7d ldr r3, [pc, #500] ; (80015cc ) 80013d8: 689b ldr r3, [r3, #8] 80013da: f023 02f0 bic.w r2, r3, #240 ; 0xf0 80013de: 687b ldr r3, [r7, #4] 80013e0: 689b ldr r3, [r3, #8] 80013e2: 497a ldr r1, [pc, #488] ; (80015cc ) 80013e4: 4313 orrs r3, r2 80013e6: 608b str r3, [r1, #8] } /*------------------------- SYSCLK Configuration ---------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) 80013e8: 687b ldr r3, [r7, #4] 80013ea: 681b ldr r3, [r3, #0] 80013ec: f003 0301 and.w r3, r3, #1 80013f0: 2b00 cmp r3, #0 80013f2: f000 808e beq.w 8001512 { assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); /* HSE is selected as System Clock Source */ if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) 80013f6: 687b ldr r3, [r7, #4] 80013f8: 685b ldr r3, [r3, #4] 80013fa: 2b02 cmp r3, #2 80013fc: d107 bne.n 800140e { /* Check the HSE ready flag */ if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U) 80013fe: 4b73 ldr r3, [pc, #460] ; (80015cc ) 8001400: 681b ldr r3, [r3, #0] 8001402: f403 3300 and.w r3, r3, #131072 ; 0x20000 8001406: 2b00 cmp r3, #0 8001408: d121 bne.n 800144e { return HAL_ERROR; 800140a: 2301 movs r3, #1 800140c: e0d7 b.n 80015be } } /* PLL is selected as System Clock Source */ else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) 800140e: 687b ldr r3, [r7, #4] 8001410: 685b ldr r3, [r3, #4] 8001412: 2b03 cmp r3, #3 8001414: d107 bne.n 8001426 { /* Check the PLL ready flag */ if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U) 8001416: 4b6d ldr r3, [pc, #436] ; (80015cc ) 8001418: 681b ldr r3, [r3, #0] 800141a: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 800141e: 2b00 cmp r3, #0 8001420: d115 bne.n 800144e { return HAL_ERROR; 8001422: 2301 movs r3, #1 8001424: e0cb b.n 80015be } } /* HSI is selected as System Clock Source */ else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI) 8001426: 687b ldr r3, [r7, #4] 8001428: 685b ldr r3, [r3, #4] 800142a: 2b01 cmp r3, #1 800142c: d107 bne.n 800143e { /* Check the HSI ready flag */ if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) 800142e: 4b67 ldr r3, [pc, #412] ; (80015cc ) 8001430: 681b ldr r3, [r3, #0] 8001432: f003 0302 and.w r3, r3, #2 8001436: 2b00 cmp r3, #0 8001438: d109 bne.n 800144e { return HAL_ERROR; 800143a: 2301 movs r3, #1 800143c: e0bf b.n 80015be } /* MSI is selected as System Clock Source */ else { /* Check the MSI ready flag */ if(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) == 0U) 800143e: 4b63 ldr r3, [pc, #396] ; (80015cc ) 8001440: 681b ldr r3, [r3, #0] 8001442: f403 7300 and.w r3, r3, #512 ; 0x200 8001446: 2b00 cmp r3, #0 8001448: d101 bne.n 800144e { return HAL_ERROR; 800144a: 2301 movs r3, #1 800144c: e0b7 b.n 80015be } } __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource); 800144e: 4b5f ldr r3, [pc, #380] ; (80015cc ) 8001450: 689b ldr r3, [r3, #8] 8001452: f023 0203 bic.w r2, r3, #3 8001456: 687b ldr r3, [r7, #4] 8001458: 685b ldr r3, [r3, #4] 800145a: 495c ldr r1, [pc, #368] ; (80015cc ) 800145c: 4313 orrs r3, r2 800145e: 608b str r3, [r1, #8] /* Get Start Tick */ tickstart = HAL_GetTick(); 8001460: f7ff f988 bl 8000774 8001464: 60f8 str r0, [r7, #12] if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) 8001466: 687b ldr r3, [r7, #4] 8001468: 685b ldr r3, [r3, #4] 800146a: 2b02 cmp r3, #2 800146c: d112 bne.n 8001494 { while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE) 800146e: e00a b.n 8001486 { if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) 8001470: f7ff f980 bl 8000774 8001474: 4602 mov r2, r0 8001476: 68fb ldr r3, [r7, #12] 8001478: 1ad3 subs r3, r2, r3 800147a: f241 3288 movw r2, #5000 ; 0x1388 800147e: 4293 cmp r3, r2 8001480: d901 bls.n 8001486 { return HAL_TIMEOUT; 8001482: 2303 movs r3, #3 8001484: e09b b.n 80015be while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE) 8001486: 4b51 ldr r3, [pc, #324] ; (80015cc ) 8001488: 689b ldr r3, [r3, #8] 800148a: f003 030c and.w r3, r3, #12 800148e: 2b08 cmp r3, #8 8001490: d1ee bne.n 8001470 8001492: e03e b.n 8001512 } } } else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) 8001494: 687b ldr r3, [r7, #4] 8001496: 685b ldr r3, [r3, #4] 8001498: 2b03 cmp r3, #3 800149a: d112 bne.n 80014c2 { while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) 800149c: e00a b.n 80014b4 { if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) 800149e: f7ff f969 bl 8000774 80014a2: 4602 mov r2, r0 80014a4: 68fb ldr r3, [r7, #12] 80014a6: 1ad3 subs r3, r2, r3 80014a8: f241 3288 movw r2, #5000 ; 0x1388 80014ac: 4293 cmp r3, r2 80014ae: d901 bls.n 80014b4 { return HAL_TIMEOUT; 80014b0: 2303 movs r3, #3 80014b2: e084 b.n 80015be while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) 80014b4: 4b45 ldr r3, [pc, #276] ; (80015cc ) 80014b6: 689b ldr r3, [r3, #8] 80014b8: f003 030c and.w r3, r3, #12 80014bc: 2b0c cmp r3, #12 80014be: d1ee bne.n 800149e 80014c0: e027 b.n 8001512 } } } else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI) 80014c2: 687b ldr r3, [r7, #4] 80014c4: 685b ldr r3, [r3, #4] 80014c6: 2b01 cmp r3, #1 80014c8: d11d bne.n 8001506 { while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI) 80014ca: e00a b.n 80014e2 { if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) 80014cc: f7ff f952 bl 8000774 80014d0: 4602 mov r2, r0 80014d2: 68fb ldr r3, [r7, #12] 80014d4: 1ad3 subs r3, r2, r3 80014d6: f241 3288 movw r2, #5000 ; 0x1388 80014da: 4293 cmp r3, r2 80014dc: d901 bls.n 80014e2 { return HAL_TIMEOUT; 80014de: 2303 movs r3, #3 80014e0: e06d b.n 80015be while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI) 80014e2: 4b3a ldr r3, [pc, #232] ; (80015cc ) 80014e4: 689b ldr r3, [r3, #8] 80014e6: f003 030c and.w r3, r3, #12 80014ea: 2b04 cmp r3, #4 80014ec: d1ee bne.n 80014cc 80014ee: e010 b.n 8001512 } else { while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_MSI) { if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) 80014f0: f7ff f940 bl 8000774 80014f4: 4602 mov r2, r0 80014f6: 68fb ldr r3, [r7, #12] 80014f8: 1ad3 subs r3, r2, r3 80014fa: f241 3288 movw r2, #5000 ; 0x1388 80014fe: 4293 cmp r3, r2 8001500: d901 bls.n 8001506 { return HAL_TIMEOUT; 8001502: 2303 movs r3, #3 8001504: e05b b.n 80015be while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_MSI) 8001506: 4b31 ldr r3, [pc, #196] ; (80015cc ) 8001508: 689b ldr r3, [r3, #8] 800150a: f003 030c and.w r3, r3, #12 800150e: 2b00 cmp r3, #0 8001510: d1ee bne.n 80014f0 } } } } /* Decreasing the number of wait states because of lower CPU frequency */ if(FLatency < __HAL_FLASH_GET_LATENCY()) 8001512: 4b2d ldr r3, [pc, #180] ; (80015c8 ) 8001514: 681b ldr r3, [r3, #0] 8001516: f003 0301 and.w r3, r3, #1 800151a: 683a ldr r2, [r7, #0] 800151c: 429a cmp r2, r3 800151e: d219 bcs.n 8001554 { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 8001520: 683b ldr r3, [r7, #0] 8001522: 2b01 cmp r3, #1 8001524: d105 bne.n 8001532 8001526: 4b28 ldr r3, [pc, #160] ; (80015c8 ) 8001528: 681b ldr r3, [r3, #0] 800152a: 4a27 ldr r2, [pc, #156] ; (80015c8 ) 800152c: f043 0304 orr.w r3, r3, #4 8001530: 6013 str r3, [r2, #0] 8001532: 4b25 ldr r3, [pc, #148] ; (80015c8 ) 8001534: 681b ldr r3, [r3, #0] 8001536: f023 0201 bic.w r2, r3, #1 800153a: 4923 ldr r1, [pc, #140] ; (80015c8 ) 800153c: 683b ldr r3, [r7, #0] 800153e: 4313 orrs r3, r2 8001540: 600b str r3, [r1, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if(__HAL_FLASH_GET_LATENCY() != FLatency) 8001542: 4b21 ldr r3, [pc, #132] ; (80015c8 ) 8001544: 681b ldr r3, [r3, #0] 8001546: f003 0301 and.w r3, r3, #1 800154a: 683a ldr r2, [r7, #0] 800154c: 429a cmp r2, r3 800154e: d001 beq.n 8001554 { return HAL_ERROR; 8001550: 2301 movs r3, #1 8001552: e034 b.n 80015be } } /*-------------------------- PCLK1 Configuration ---------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 8001554: 687b ldr r3, [r7, #4] 8001556: 681b ldr r3, [r3, #0] 8001558: f003 0304 and.w r3, r3, #4 800155c: 2b00 cmp r3, #0 800155e: d008 beq.n 8001572 { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider); 8001560: 4b1a ldr r3, [pc, #104] ; (80015cc ) 8001562: 689b ldr r3, [r3, #8] 8001564: f423 62e0 bic.w r2, r3, #1792 ; 0x700 8001568: 687b ldr r3, [r7, #4] 800156a: 68db ldr r3, [r3, #12] 800156c: 4917 ldr r1, [pc, #92] ; (80015cc ) 800156e: 4313 orrs r3, r2 8001570: 608b str r3, [r1, #8] } /*-------------------------- PCLK2 Configuration ---------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) 8001572: 687b ldr r3, [r7, #4] 8001574: 681b ldr r3, [r3, #0] 8001576: f003 0308 and.w r3, r3, #8 800157a: 2b00 cmp r3, #0 800157c: d009 beq.n 8001592 { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U)); 800157e: 4b13 ldr r3, [pc, #76] ; (80015cc ) 8001580: 689b ldr r3, [r3, #8] 8001582: f423 5260 bic.w r2, r3, #14336 ; 0x3800 8001586: 687b ldr r3, [r7, #4] 8001588: 691b ldr r3, [r3, #16] 800158a: 00db lsls r3, r3, #3 800158c: 490f ldr r1, [pc, #60] ; (80015cc ) 800158e: 4313 orrs r3, r2 8001590: 608b str r3, [r1, #8] } /* Update the SystemCoreClock global variable */ SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_Pos]; 8001592: f000 f823 bl 80015dc 8001596: 4601 mov r1, r0 8001598: 4b0c ldr r3, [pc, #48] ; (80015cc ) 800159a: 689b ldr r3, [r3, #8] 800159c: 091b lsrs r3, r3, #4 800159e: f003 030f and.w r3, r3, #15 80015a2: 4a0b ldr r2, [pc, #44] ; (80015d0 ) 80015a4: 5cd3 ldrb r3, [r2, r3] 80015a6: fa21 f303 lsr.w r3, r1, r3 80015aa: 4a0a ldr r2, [pc, #40] ; (80015d4 ) 80015ac: 6013 str r3, [r2, #0] /* Configure the source of time base considering new system clocks settings*/ status = HAL_InitTick(uwTickPrio); 80015ae: 4b0a ldr r3, [pc, #40] ; (80015d8 ) 80015b0: 681b ldr r3, [r3, #0] 80015b2: 4618 mov r0, r3 80015b4: f7ff f892 bl 80006dc 80015b8: 4603 mov r3, r0 80015ba: 72fb strb r3, [r7, #11] return status; 80015bc: 7afb ldrb r3, [r7, #11] } 80015be: 4618 mov r0, r3 80015c0: 3710 adds r7, #16 80015c2: 46bd mov sp, r7 80015c4: bd80 pop {r7, pc} 80015c6: bf00 nop 80015c8: 40023c00 .word 0x40023c00 80015cc: 40023800 .word 0x40023800 80015d0: 0800185c .word 0x0800185c 80015d4: 20000000 .word 0x20000000 80015d8: 20000004 .word 0x20000004 080015dc : * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect. * * @retval SYSCLK frequency */ uint32_t HAL_RCC_GetSysClockFreq(void) { 80015dc: b5f0 push {r4, r5, r6, r7, lr} 80015de: b087 sub sp, #28 80015e0: af00 add r7, sp, #0 uint32_t tmpreg, pllm, plld, pllvco, msiclkrange, sysclockfreq; tmpreg = RCC->CFGR; 80015e2: 4b4b ldr r3, [pc, #300] ; (8001710 ) 80015e4: 689b ldr r3, [r3, #8] 80015e6: 60fb str r3, [r7, #12] /* Get SYSCLK source -------------------------------------------------------*/ switch (tmpreg & RCC_CFGR_SWS) 80015e8: 68fb ldr r3, [r7, #12] 80015ea: f003 030c and.w r3, r3, #12 80015ee: 2b08 cmp r3, #8 80015f0: d006 beq.n 8001600 80015f2: 2b0c cmp r3, #12 80015f4: d007 beq.n 8001606 80015f6: 2b04 cmp r3, #4 80015f8: d176 bne.n 80016e8 { case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */ { sysclockfreq = HSI_VALUE; 80015fa: 4b46 ldr r3, [pc, #280] ; (8001714 ) 80015fc: 613b str r3, [r7, #16] break; 80015fe: e081 b.n 8001704 } case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */ { sysclockfreq = HSE_VALUE; 8001600: 4b45 ldr r3, [pc, #276] ; (8001718 ) 8001602: 613b str r3, [r7, #16] break; 8001604: e07e b.n 8001704 } case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */ { pllm = PLLMulTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMUL) >> RCC_CFGR_PLLMUL_Pos]; 8001606: 68fb ldr r3, [r7, #12] 8001608: 0c9b lsrs r3, r3, #18 800160a: f003 030f and.w r3, r3, #15 800160e: 4a43 ldr r2, [pc, #268] ; (800171c ) 8001610: 5cd3 ldrb r3, [r2, r3] 8001612: 60bb str r3, [r7, #8] plld = ((uint32_t)(tmpreg & RCC_CFGR_PLLDIV) >> RCC_CFGR_PLLDIV_Pos) + 1U; 8001614: 68fb ldr r3, [r7, #12] 8001616: 0d9b lsrs r3, r3, #22 8001618: f003 0303 and.w r3, r3, #3 800161c: 3301 adds r3, #1 800161e: 607b str r3, [r7, #4] if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI) 8001620: 4b3b ldr r3, [pc, #236] ; (8001710 ) 8001622: 689b ldr r3, [r3, #8] 8001624: f403 3380 and.w r3, r3, #65536 ; 0x10000 8001628: 2b00 cmp r3, #0 800162a: d019 beq.n 8001660 { /* HSE used as PLL clock source */ pllvco = (uint32_t)(((uint64_t)HSE_VALUE * (uint64_t)pllm) / (uint64_t)plld); 800162c: 68bb ldr r3, [r7, #8] 800162e: f04f 0400 mov.w r4, #0 8001632: 4a39 ldr r2, [pc, #228] ; (8001718 ) 8001634: fb02 f104 mul.w r1, r2, r4 8001638: 2200 movs r2, #0 800163a: fb02 f203 mul.w r2, r2, r3 800163e: 440a add r2, r1 8001640: 4935 ldr r1, [pc, #212] ; (8001718 ) 8001642: fba3 0101 umull r0, r1, r3, r1 8001646: 1853 adds r3, r2, r1 8001648: 4619 mov r1, r3 800164a: 687b ldr r3, [r7, #4] 800164c: f04f 0400 mov.w r4, #0 8001650: 461a mov r2, r3 8001652: 4623 mov r3, r4 8001654: f7fe fd92 bl 800017c <__aeabi_uldivmod> 8001658: 4603 mov r3, r0 800165a: 460c mov r4, r1 800165c: 617b str r3, [r7, #20] 800165e: e040 b.n 80016e2 } else { /* HSI used as PLL clock source */ pllvco = (uint32_t)(((uint64_t)HSI_VALUE * (uint64_t)pllm) / (uint64_t)plld); 8001660: 68bb ldr r3, [r7, #8] 8001662: 461d mov r5, r3 8001664: f04f 0600 mov.w r6, #0 8001668: 4629 mov r1, r5 800166a: 4632 mov r2, r6 800166c: f04f 0300 mov.w r3, #0 8001670: f04f 0400 mov.w r4, #0 8001674: 0154 lsls r4, r2, #5 8001676: ea44 64d1 orr.w r4, r4, r1, lsr #27 800167a: 014b lsls r3, r1, #5 800167c: 4619 mov r1, r3 800167e: 4622 mov r2, r4 8001680: 1b49 subs r1, r1, r5 8001682: eb62 0206 sbc.w r2, r2, r6 8001686: f04f 0300 mov.w r3, #0 800168a: f04f 0400 mov.w r4, #0 800168e: 0194 lsls r4, r2, #6 8001690: ea44 6491 orr.w r4, r4, r1, lsr #26 8001694: 018b lsls r3, r1, #6 8001696: 1a5b subs r3, r3, r1 8001698: eb64 0402 sbc.w r4, r4, r2 800169c: f04f 0100 mov.w r1, #0 80016a0: f04f 0200 mov.w r2, #0 80016a4: 00e2 lsls r2, r4, #3 80016a6: ea42 7253 orr.w r2, r2, r3, lsr #29 80016aa: 00d9 lsls r1, r3, #3 80016ac: 460b mov r3, r1 80016ae: 4614 mov r4, r2 80016b0: 195b adds r3, r3, r5 80016b2: eb44 0406 adc.w r4, r4, r6 80016b6: f04f 0100 mov.w r1, #0 80016ba: f04f 0200 mov.w r2, #0 80016be: 02a2 lsls r2, r4, #10 80016c0: ea42 5293 orr.w r2, r2, r3, lsr #22 80016c4: 0299 lsls r1, r3, #10 80016c6: 460b mov r3, r1 80016c8: 4614 mov r4, r2 80016ca: 4618 mov r0, r3 80016cc: 4621 mov r1, r4 80016ce: 687b ldr r3, [r7, #4] 80016d0: f04f 0400 mov.w r4, #0 80016d4: 461a mov r2, r3 80016d6: 4623 mov r3, r4 80016d8: f7fe fd50 bl 800017c <__aeabi_uldivmod> 80016dc: 4603 mov r3, r0 80016de: 460c mov r4, r1 80016e0: 617b str r3, [r7, #20] } sysclockfreq = pllvco; 80016e2: 697b ldr r3, [r7, #20] 80016e4: 613b str r3, [r7, #16] break; 80016e6: e00d b.n 8001704 } case RCC_SYSCLKSOURCE_STATUS_MSI: /* MSI used as system clock source */ default: /* MSI used as system clock */ { msiclkrange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE ) >> RCC_ICSCR_MSIRANGE_Pos; 80016e8: 4b09 ldr r3, [pc, #36] ; (8001710 ) 80016ea: 685b ldr r3, [r3, #4] 80016ec: 0b5b lsrs r3, r3, #13 80016ee: f003 0307 and.w r3, r3, #7 80016f2: 603b str r3, [r7, #0] sysclockfreq = (32768U * (1UL << (msiclkrange + 1U))); 80016f4: 683b ldr r3, [r7, #0] 80016f6: 3301 adds r3, #1 80016f8: f44f 4200 mov.w r2, #32768 ; 0x8000 80016fc: fa02 f303 lsl.w r3, r2, r3 8001700: 613b str r3, [r7, #16] break; 8001702: bf00 nop } } return sysclockfreq; 8001704: 693b ldr r3, [r7, #16] } 8001706: 4618 mov r0, r3 8001708: 371c adds r7, #28 800170a: 46bd mov sp, r7 800170c: bdf0 pop {r4, r5, r6, r7, pc} 800170e: bf00 nop 8001710: 40023800 .word 0x40023800 8001714: 00f42400 .word 0x00f42400 8001718: 016e3600 .word 0x016e3600 800171c: 08001850 .word 0x08001850 08001720 : voltage range * @param MSIrange MSI range value from RCC_MSIRANGE_0 to RCC_MSIRANGE_6 * @retval HAL status */ static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t MSIrange) { 8001720: b480 push {r7} 8001722: b087 sub sp, #28 8001724: af00 add r7, sp, #0 8001726: 6078 str r0, [r7, #4] uint32_t vos; uint32_t latency = FLASH_LATENCY_0; /* default value 0WS */ 8001728: 2300 movs r3, #0 800172a: 613b str r3, [r7, #16] /* HCLK can reach 4 MHz only if AHB prescaler = 1 */ if (READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) == RCC_SYSCLK_DIV1) 800172c: 4b29 ldr r3, [pc, #164] ; (80017d4 ) 800172e: 689b ldr r3, [r3, #8] 8001730: f003 03f0 and.w r3, r3, #240 ; 0xf0 8001734: 2b00 cmp r3, #0 8001736: d12c bne.n 8001792 { if(__HAL_RCC_PWR_IS_CLK_ENABLED()) 8001738: 4b26 ldr r3, [pc, #152] ; (80017d4 ) 800173a: 6a5b ldr r3, [r3, #36] ; 0x24 800173c: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 8001740: 2b00 cmp r3, #0 8001742: d005 beq.n 8001750 { vos = READ_BIT(PWR->CR, PWR_CR_VOS); 8001744: 4b24 ldr r3, [pc, #144] ; (80017d8 ) 8001746: 681b ldr r3, [r3, #0] 8001748: f403 53c0 and.w r3, r3, #6144 ; 0x1800 800174c: 617b str r3, [r7, #20] 800174e: e016 b.n 800177e } else { __HAL_RCC_PWR_CLK_ENABLE(); 8001750: 4b20 ldr r3, [pc, #128] ; (80017d4 ) 8001752: 6a5b ldr r3, [r3, #36] ; 0x24 8001754: 4a1f ldr r2, [pc, #124] ; (80017d4 ) 8001756: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 800175a: 6253 str r3, [r2, #36] ; 0x24 800175c: 4b1d ldr r3, [pc, #116] ; (80017d4 ) 800175e: 6a5b ldr r3, [r3, #36] ; 0x24 8001760: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 8001764: 60fb str r3, [r7, #12] 8001766: 68fb ldr r3, [r7, #12] vos = READ_BIT(PWR->CR, PWR_CR_VOS); 8001768: 4b1b ldr r3, [pc, #108] ; (80017d8 ) 800176a: 681b ldr r3, [r3, #0] 800176c: f403 53c0 and.w r3, r3, #6144 ; 0x1800 8001770: 617b str r3, [r7, #20] __HAL_RCC_PWR_CLK_DISABLE(); 8001772: 4b18 ldr r3, [pc, #96] ; (80017d4 ) 8001774: 6a5b ldr r3, [r3, #36] ; 0x24 8001776: 4a17 ldr r2, [pc, #92] ; (80017d4 ) 8001778: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000 800177c: 6253 str r3, [r2, #36] ; 0x24 } /* Check if need to set latency 1 only for Range 3 & HCLK = 4MHz */ if((vos == PWR_REGULATOR_VOLTAGE_SCALE3) && (MSIrange == RCC_MSIRANGE_6)) 800177e: 697b ldr r3, [r7, #20] 8001780: f5b3 5fc0 cmp.w r3, #6144 ; 0x1800 8001784: d105 bne.n 8001792 8001786: 687b ldr r3, [r7, #4] 8001788: f5b3 4f40 cmp.w r3, #49152 ; 0xc000 800178c: d101 bne.n 8001792 { latency = FLASH_LATENCY_1; /* 1WS */ 800178e: 2301 movs r3, #1 8001790: 613b str r3, [r7, #16] } } __HAL_FLASH_SET_LATENCY(latency); 8001792: 693b ldr r3, [r7, #16] 8001794: 2b01 cmp r3, #1 8001796: d105 bne.n 80017a4 8001798: 4b10 ldr r3, [pc, #64] ; (80017dc ) 800179a: 681b ldr r3, [r3, #0] 800179c: 4a0f ldr r2, [pc, #60] ; (80017dc ) 800179e: f043 0304 orr.w r3, r3, #4 80017a2: 6013 str r3, [r2, #0] 80017a4: 4b0d ldr r3, [pc, #52] ; (80017dc ) 80017a6: 681b ldr r3, [r3, #0] 80017a8: f023 0201 bic.w r2, r3, #1 80017ac: 490b ldr r1, [pc, #44] ; (80017dc ) 80017ae: 693b ldr r3, [r7, #16] 80017b0: 4313 orrs r3, r2 80017b2: 600b str r3, [r1, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if(__HAL_FLASH_GET_LATENCY() != latency) 80017b4: 4b09 ldr r3, [pc, #36] ; (80017dc ) 80017b6: 681b ldr r3, [r3, #0] 80017b8: f003 0301 and.w r3, r3, #1 80017bc: 693a ldr r2, [r7, #16] 80017be: 429a cmp r2, r3 80017c0: d001 beq.n 80017c6 { return HAL_ERROR; 80017c2: 2301 movs r3, #1 80017c4: e000 b.n 80017c8 } return HAL_OK; 80017c6: 2300 movs r3, #0 } 80017c8: 4618 mov r0, r3 80017ca: 371c adds r7, #28 80017cc: 46bd mov sp, r7 80017ce: bc80 pop {r7} 80017d0: 4770 bx lr 80017d2: bf00 nop 80017d4: 40023800 .word 0x40023800 80017d8: 40007000 .word 0x40007000 80017dc: 40023c00 .word 0x40023c00 080017e0 <__libc_init_array>: 80017e0: b570 push {r4, r5, r6, lr} 80017e2: 2500 movs r5, #0 80017e4: 4e0c ldr r6, [pc, #48] ; (8001818 <__libc_init_array+0x38>) 80017e6: 4c0d ldr r4, [pc, #52] ; (800181c <__libc_init_array+0x3c>) 80017e8: 1ba4 subs r4, r4, r6 80017ea: 10a4 asrs r4, r4, #2 80017ec: 42a5 cmp r5, r4 80017ee: d109 bne.n 8001804 <__libc_init_array+0x24> 80017f0: f000 f822 bl 8001838 <_init> 80017f4: 2500 movs r5, #0 80017f6: 4e0a ldr r6, [pc, #40] ; (8001820 <__libc_init_array+0x40>) 80017f8: 4c0a ldr r4, [pc, #40] ; (8001824 <__libc_init_array+0x44>) 80017fa: 1ba4 subs r4, r4, r6 80017fc: 10a4 asrs r4, r4, #2 80017fe: 42a5 cmp r5, r4 8001800: d105 bne.n 800180e <__libc_init_array+0x2e> 8001802: bd70 pop {r4, r5, r6, pc} 8001804: f856 3025 ldr.w r3, [r6, r5, lsl #2] 8001808: 4798 blx r3 800180a: 3501 adds r5, #1 800180c: e7ee b.n 80017ec <__libc_init_array+0xc> 800180e: f856 3025 ldr.w r3, [r6, r5, lsl #2] 8001812: 4798 blx r3 8001814: 3501 adds r5, #1 8001816: e7f2 b.n 80017fe <__libc_init_array+0x1e> 8001818: 08001874 .word 0x08001874 800181c: 08001874 .word 0x08001874 8001820: 08001874 .word 0x08001874 8001824: 08001878 .word 0x08001878 08001828 : 8001828: 4603 mov r3, r0 800182a: 4402 add r2, r0 800182c: 4293 cmp r3, r2 800182e: d100 bne.n 8001832 8001830: 4770 bx lr 8001832: f803 1b01 strb.w r1, [r3], #1 8001836: e7f9 b.n 800182c 08001838 <_init>: 8001838: b5f8 push {r3, r4, r5, r6, r7, lr} 800183a: bf00 nop 800183c: bcf8 pop {r3, r4, r5, r6, r7} 800183e: bc08 pop {r3} 8001840: 469e mov lr, r3 8001842: 4770 bx lr 08001844 <_fini>: 8001844: b5f8 push {r3, r4, r5, r6, r7, lr} 8001846: bf00 nop 8001848: bcf8 pop {r3, r4, r5, r6, r7} 800184a: bc08 pop {r3} 800184c: 469e mov lr, r3 800184e: 4770 bx lr